forked from M-Labs/artiq
sayma: SYSREF setup/hold validation demonstration
This also removes the standalone target as the ISERDES used for setup/hold check requires the fine RTIO clock, which in turn requires a DRTIO transceiver due to the Ultrascale TPWS bug.
This commit is contained in:
parent
3356717316
commit
cb04230f86
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@ -1,13 +1,24 @@
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use board_misoc::{csr, config};
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use board_misoc::{csr, clock, config};
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use hmc830_7043::hmc7043;
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use ad9154;
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fn sysref_sh_error() -> bool {
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unsafe {
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csr::sysref_sampler::sh_error_reset_write(1);
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clock::spin_us(1);
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csr::sysref_sampler::sh_error_reset_write(0);
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clock::spin_us(10);
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csr::sysref_sampler::sh_error_read() != 0
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}
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}
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pub fn sysref_auto_rtio_align() -> Result<(), &'static str> {
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for _ in 0..256 {
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hmc7043::sysref_slip();
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let dt = unsafe { csr::sysref_ddmtd::dt_read() };
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info!("dt={}", dt);
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let sh_error = sysref_sh_error();
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info!("dt={} sysref_sh_error={}", dt, sh_error);
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}
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Ok(())
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}
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@ -22,7 +22,6 @@ class UltrascaleCRG(Module, AutoCSR):
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def __init__(self, platform, use_rtio_clock=False):
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self.ibuf_disable = CSRStorage(reset=1)
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self.jreset = CSRStorage(reset=1)
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self.jref = Signal()
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self.refclk = Signal()
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self.clock_domains.cd_jesd = ClockDomain()
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@ -42,23 +41,6 @@ class UltrascaleCRG(Module, AutoCSR):
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else:
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self.specials += Instance("BUFG_GT", i_I=refclk2, o_O=self.cd_jesd.clk)
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jref = platform.request("dac_sysref")
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jref_se = Signal()
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jref_r = Signal()
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self.specials += [
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Instance("IBUFDS_IBUFDISABLE",
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p_USE_IBUFDISABLE="TRUE", p_SIM_DEVICE="ULTRASCALE",
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i_IBUFDISABLE=self.ibuf_disable.storage,
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i_I=jref.p, i_IB=jref.n,
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o_O=jref_se),
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# SYSREF normally meets s/h at the FPGA, except during margin
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# scan and before full initialization.
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# Be paranoid and use a double-register anyway.
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Instance("FD", i_C=ClockSignal("jesd"), i_D=jref_se, o_Q=jref_r,
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attr={("IOB", "TRUE")}),
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Instance("FD", i_C=ClockSignal("jesd"), i_D=jref_r, o_Q=self.jref)
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]
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PhyPads = namedtuple("PhyPads", "txp txn")
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@ -90,7 +72,6 @@ class UltrascaleTX(Module, AutoCSR):
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phys, settings, converter_data_width=64)
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self.submodules.control = JESD204BCoreTXControl(self.core)
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self.core.register_jsync(platform.request("dac_sync", dac))
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self.core.register_jref(jesd_crg.jref)
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# See "Digital femtosecond time difference circuit for CERN's timing system"
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@ -157,3 +138,60 @@ class DDMTD(Module, AutoCSR):
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bsync.i.eq(result),
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self.dt.status.eq(bsync.o)
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]
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# This assumes:
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# * coarse RTIO frequency = 16*SYSREF frequency
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# * fine RTIO frequency (rtiox) = 2*RTIO frequency
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# * JESD and coarse RTIO clocks are the same
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# (only reset may differ).
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#
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# Look at the 4 LSBs of the coarse RTIO timestamp counter
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# to determine SYSREF phase.
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class SysrefSampler(Module, AutoCSR):
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def __init__(self, sysref_pads, coarse_ts):
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self.sh_error = CSRStatus()
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self.sh_error_reset = CSRStorage()
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self.sample_result = CSRStatus()
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self.jref = Signal()
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# # #
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sysref_se = Signal()
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sysref_oversample = Signal(4)
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self.specials += [
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Instance("IBUFDS", i_I=sysref_pads.p, i_IB=sysref_pads.n, o_O=sysref_se),
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Instance("ISERDESE3",
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p_IS_CLK_INVERTED=0,
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p_IS_CLK_B_INVERTED=1,
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p_DATA_WIDTH=4,
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i_D=sysref_se,
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i_RST=ResetSignal("rtio"),
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i_FIFO_RD_EN=0,
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i_CLK=ClockSignal("rtiox"),
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i_CLK_B=ClockSignal("rtiox"), # locally inverted
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i_CLKDIV=ClockSignal("rtio"),
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o_Q=sysref_oversample)
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]
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self.comb += self.jref.eq(sysref_oversample[1])
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sh_error = Signal()
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sh_error_reset = Signal()
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self.sync.rtio += [
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If(~( (sysref_oversample[0] == sysref_oversample[1])
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& (sysref_oversample[1] == sysref_oversample[2])),
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sh_error.eq(1)
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),
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If(sh_error_reset, sh_error.eq(0))
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]
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self.specials += [
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MultiReg(self.sh_error_reset.storage, sh_error_reset, "rtio"),
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MultiReg(sh_error, self.sh_error.status)
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]
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sample = Signal()
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self.sync.rtio += If(coarse_ts[:4] == 0, sample.eq(self.jref))
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self.specials += MultiReg(sample, self.sample_result.status)
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@ -114,119 +114,6 @@ class RTMCommon:
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self.add_wb_slave(self.mem_map["serwb"], 8192, serwb_core.etherbone.wishbone.bus)
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class Standalone(MiniSoC, AMPSoC, RTMCommon):
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"""
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Local DAC/SAWG channels only.
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"""
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mem_map = {
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"cri_con": 0x10000000,
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"rtio": 0x11000000,
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"rtio_dma": 0x12000000,
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"serwb": 0x13000000,
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"mailbox": 0x70000000
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}
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mem_map.update(MiniSoC.mem_map)
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def __init__(self, with_sawg, **kwargs):
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MiniSoC.__init__(self,
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cpu_type="or1k",
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sdram_controller_type="minicon",
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l2_size=128*1024,
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ethmac_nrxslots=4,
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ethmac_ntxslots=4,
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**kwargs)
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AMPSoC.__init__(self)
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RTMCommon.__init__(self)
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add_identifier(self, suffix=".without-sawg" if not with_sawg else "")
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self.config["HMC830_REF"] = "100"
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platform = self.platform
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self.submodules.si5324_rst_n = gpio.GPIOOut(platform.request("si5324").rst_n)
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self.csr_devices.append("si5324_rst_n")
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i2c = self.platform.request("i2c")
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self.submodules.i2c = gpio.GPIOTristate([i2c.scl, i2c.sda])
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self.csr_devices.append("i2c")
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self.config["I2C_BUS_COUNT"] = 1
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self.config["HAS_SI5324"] = None
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self.config["SI5324_AS_SYNTHESIZER"] = None
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self.config["SI5324_SAYMA_REF"] = None
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# ensure pins are properly biased and terminated
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si5324_clkout = platform.request("si5324_clkout", 0)
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self.specials += Instance(
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"IBUFDS_GTE3", i_CEB=0, i_I=si5324_clkout.p, i_IB=si5324_clkout.n,
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attr={("DONT_TOUCH", "true")})
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# RTIO
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rtio_channels = []
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for i in range(4):
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phy = ttl_simple.Output(platform.request("user_led", i))
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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# To work around Ultrascale issues (https://www.xilinx.com/support/answers/67885.html),
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# we generate the multiplied RTIO clock using the DRTIO GTH transceiver.
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# Since there is no DRTIO here and therefoere no multiplied clock, we use ttl_simple.
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sma_io = platform.request("sma_io", 0)
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self.comb += sma_io.direction.eq(1)
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phy = ttl_simple.Output(sma_io.level)
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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sma_io = platform.request("sma_io", 1)
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self.comb += sma_io.direction.eq(0)
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phy = ttl_simple.InOut(sma_io.level)
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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self.submodules.ad9154_crg = jesd204_tools.UltrascaleCRG(platform)
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if with_sawg:
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cls = AD9154
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else:
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cls = AD9154NoSAWG
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self.submodules.ad9154_0 = cls(platform, self.crg, self.ad9154_crg, 0)
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self.submodules.ad9154_1 = cls(platform, self.crg, self.ad9154_crg, 1)
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self.csr_devices.append("ad9154_crg")
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self.csr_devices.append("ad9154_0")
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self.csr_devices.append("ad9154_1")
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self.config["HAS_AD9154"] = None
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self.add_csr_group("ad9154", ["ad9154_0", "ad9154_1"])
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self.config["RTIO_FIRST_SAWG_CHANNEL"] = len(rtio_channels)
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rtio_channels.extend(rtio.Channel.from_phy(phy)
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for sawg in self.ad9154_0.sawgs +
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self.ad9154_1.sawgs
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for phy in sawg.phys)
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self.config["HAS_RTIO_LOG"] = None
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self.config["RTIO_LOG_CHANNEL"] = len(rtio_channels)
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rtio_channels.append(rtio.LogChannel())
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self.clock_domains.cd_rtio = ClockDomain()
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self.comb += [
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self.cd_rtio.clk.eq(ClockSignal("jesd")),
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self.cd_rtio.rst.eq(ResetSignal("jesd"))
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]
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self.submodules.rtio_tsc = rtio.TSC("async")
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self.submodules.rtio_core = rtio.Core(self.rtio_tsc, rtio_channels)
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self.csr_devices.append("rtio_core")
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self.submodules.rtio = rtio.KernelInitiator(self.rtio_tsc)
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self.submodules.rtio_dma = ClockDomainsRenamer("sys_kernel")(
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rtio.DMA(self.get_native_sdram_if()))
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self.register_kernel_cpu_csrdevice("rtio")
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self.register_kernel_cpu_csrdevice("rtio_dma")
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self.submodules.cri_con = rtio.CRIInterconnectShared(
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[self.rtio.cri, self.rtio_dma.cri],
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[self.rtio_core.cri])
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self.register_kernel_cpu_csrdevice("cri_con")
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self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)
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self.csr_devices.append("rtio_moninj")
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self.submodules.rtio_analyzer = rtio.Analyzer(self.rtio_tsc, self.rtio_core.cri,
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self.get_native_sdram_if())
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self.csr_devices.append("rtio_analyzer")
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self.submodules.sysref_ddmtd = jesd204_tools.DDMTD(platform.request("adc_sysref"))
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self.csr_devices.append("sysref_ddmtd")
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class MasterDAC(MiniSoC, AMPSoC, RTMCommon):
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"""
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DRTIO master with local DAC/SAWG channels.
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@ -396,6 +283,11 @@ class MasterDAC(MiniSoC, AMPSoC, RTMCommon):
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self.submodules.sysref_ddmtd = jesd204_tools.DDMTD(platform.request("adc_sysref"))
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self.csr_devices.append("sysref_ddmtd")
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self.submodules.sysref_sampler = jesd204_tools.SysrefSampler(
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platform.request("dac_sysref"), self.rtio_tsc.coarse_ts)
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self.csr_devices.append("sysref_sampler")
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self.ad9154_0.jesd.core.register_jref(self.sysref_sampler.jref)
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self.ad9154_1.jesd.core.register_jref(self.sysref_sampler.jref)
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def workaround_us_lvds_tristate(platform):
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@ -684,6 +576,11 @@ class Satellite(BaseSoC, RTMCommon):
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self.submodules.sysref_ddmtd = jesd204_tools.DDMTD(platform.request("adc_sysref"))
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self.csr_devices.append("sysref_ddmtd")
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self.submodules.sysref_sampler = jesd204_tools.SysrefSampler(
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platform.request("dac_sysref"), self.rtio_tsc.coarse_ts)
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self.csr_devices.append("sysref_sampler")
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self.ad9154_0.jesd.core.register_jref(self.sysref_sampler.jref)
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self.ad9154_1.jesd.core.register_jref(self.sysref_sampler.jref)
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rtio_clk_period = 1e9/rtio_clk_freq
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gth = self.drtio_transceiver.gths[0]
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@ -700,9 +597,8 @@ def main():
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builder_args(parser)
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soc_sdram_args(parser)
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parser.set_defaults(output_dir="artiq_sayma")
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parser.add_argument("-V", "--variant", default="standalone",
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help="variant: "
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"standalone/masterdac/master/satellite "
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parser.add_argument("-V", "--variant", default="masterdac",
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help="variant: masterdac/master/satellite "
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"(default: %(default)s)")
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parser.add_argument("--rtm-csr-csv",
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default=os.path.join("artiq_sayma", "rtm_gateware", "rtm_csr.csv"),
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@ -714,9 +610,7 @@ def main():
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args = parser.parse_args()
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variant = args.variant.lower()
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if variant == "standalone":
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cls = Standalone
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elif variant == "masterdac":
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if variant == "masterdac":
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cls = MasterDAC
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elif variant == "master":
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cls = lambda with_sawg, **kwargs: Master(**kwargs)
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