forked from M-Labs/artiq
sayma_rtm: si5324 -> cdrclkc
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parent
57a5bea43a
commit
883310d83e
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@ -82,20 +82,20 @@ class _SatelliteBase(BaseSoC):
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platform = self.platform
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disable_si5324_ibuf = Signal(reset=1)
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disable_si5324_ibuf.attr.add("no_retiming")
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si5324_clkout = platform.request("cdr_clk_clean")
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si5324_clkout_buf = Signal()
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disable_cdrclkc_ibuf = Signal(reset=1)
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disable_cdrclkc_ibuf.attr.add("no_retiming")
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cdrclkc_clkout = platform.request("cdr_clk_clean")
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cdrclkc_clkout_buf = Signal()
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self.specials += Instance("IBUFDS_GTE2",
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i_CEB=disable_si5324_ibuf,
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i_I=si5324_clkout.p, i_IB=si5324_clkout.n,
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o_O=si5324_clkout_buf)
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i_CEB=disable_cdrclkc_ibuf,
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i_I=cdrclkc_clkout.p, i_IB=cdrclkc_clkout.n,
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o_O=cdrclkc_clkout_buf)
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qpll_drtio_settings = QPLLSettings(
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refclksel=0b001,
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fbdiv=4,
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fbdiv_45=5,
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refclk_div=1)
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qpll = QPLL(si5324_clkout_buf, qpll_drtio_settings)
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qpll = QPLL(cdrclkc_clkout_buf, qpll_drtio_settings)
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self.submodules += qpll
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self.submodules.drtio_transceiver = gtp_7series.GTP(
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@ -104,7 +104,7 @@ class _SatelliteBase(BaseSoC):
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sys_clk_freq=self.clk_freq,
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rtio_clk_freq=rtio_clk_freq)
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self.csr_devices.append("drtio_transceiver")
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self.sync += disable_si5324_ibuf.eq(
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self.sync += disable_cdrclkc_ibuf.eq(
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~self.drtio_transceiver.stable_clkin.storage)
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self.submodules.rtio_tsc = rtio.TSC("sync", glbl_fine_ts_width=3)
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