forked from M-Labs/artiq
wrpll: implement ADPLLProgrammer
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d5895b8999
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8ec0f2e717
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@ -30,18 +30,17 @@ class I2CMasterMachine(Module):
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self.sda_i = Signal()
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self.submodules.cg = CEInserter()(I2CClockGen(clock_width))
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self.idle = Signal()
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self.start = Signal()
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self.stop = Signal()
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self.write = Signal()
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self.read = Signal()
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self.ack = Signal()
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self.data = Signal(8)
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self.idle = Signal()
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###
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busy = Signal()
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bits = Signal(4)
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data = Signal(8)
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fsm = CEInserter()(FSM("IDLE"))
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self.submodules += fsm
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@ -55,10 +54,8 @@ class I2CMasterMachine(Module):
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NextState("STOP0"),
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).Elif(self.write,
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NextValue(bits, 8),
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NextState("WRITE0"),
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).Elif(self.read,
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NextValue(bits, 8),
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NextState("READ0"),
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NextValue(data, self.data),
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NextState("WRITE0")
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)
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)
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@ -93,13 +90,13 @@ class I2CMasterMachine(Module):
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NextValue(self.sda_o, 1),
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NextState("READACK0"),
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).Else(
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NextValue(self.sda_o, self.data[7]),
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NextValue(self.sda_o, data[7]),
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NextState("WRITE1"),
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)
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)
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fsm.act("WRITE1",
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NextValue(self.scl, 1),
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NextValue(self.data[1:], self.data[:-1]),
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NextValue(data[1:], data[:-1]),
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NextValue(bits, bits - 1),
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NextState("WRITE0"),
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)
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@ -112,35 +109,9 @@ class I2CMasterMachine(Module):
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NextState("IDLE")
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)
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fsm.act("READ0",
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NextValue(self.scl, 0),
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NextState("READ1"),
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)
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fsm.act("READ1",
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NextValue(self.data[0], self.sda_i),
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NextValue(self.scl, 0),
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If(bits == 0,
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NextValue(self.sda_o, ~self.ack),
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NextState("WRITEACK0"),
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).Else(
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NextValue(self.sda_o, 1),
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NextState("READ2"),
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)
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)
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fsm.act("READ2",
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NextValue(self.scl, 1),
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NextValue(self.data[:-1], self.data[1:]),
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NextValue(bits, bits - 1),
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NextState("READ1"),
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)
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fsm.act("WRITEACK0",
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NextValue(self.scl, 1),
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NextState("IDLE"),
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)
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run = Signal()
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self.comb += [
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run.eq(self.start | self.stop | self.write | self.read),
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run.eq(self.start | self.stop | self.write),
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self.idle.eq(~run & fsm.ongoing("IDLE")),
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self.cg.ce.eq(~self.idle),
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fsm.ce.eq(run | self.cg.clk2x),
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@ -176,6 +147,80 @@ class ADPLLProgrammer(Module):
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self.sda_o.eq(master.sda_o)
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]
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fsm = FSM()
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self.submodules += fsm
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adpll = Signal.like(self.adpll)
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fsm.act("IDLE",
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If(self.stb,
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NextValue(adpll, self.adpll),
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NextState("START")
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)
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)
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fsm.act("START",
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master.start.eq(1),
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If(master.idle, NextState("DEVADDRESS"))
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)
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fsm.act("DEVADDRESS",
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master.data.eq(self.i2c_address << 1),
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master.write.eq(1),
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If(master.idle, NextState("REGADRESS"))
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)
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fsm.act("REGADRESS",
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master.data.eq(231),
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master.write.eq(1),
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If(master.idle,
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If(master.ack,
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NextState("DATA0")
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).Else(
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self.nack.eq(1),
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NextState("STOP")
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)
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)
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)
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fsm.act("DATA0",
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master.data.eq(adpll[0:8]),
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master.write.eq(1),
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If(master.idle,
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If(master.ack,
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NextState("DATA1")
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).Else(
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self.nack.eq(1),
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NextState("STOP")
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)
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)
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)
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fsm.act("DATA1",
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master.data.eq(adpll[8:16]),
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master.write.eq(1),
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If(master.idle,
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If(master.ack,
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NextState("DATA2")
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).Else(
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self.nack.eq(1),
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NextState("STOP")
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)
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)
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)
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fsm.act("DATA2",
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master.data.eq(adpll[16:24]),
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master.write.eq(1),
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If(master.idle,
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If(~master.ack, self.nack.eq(1)),
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NextState("STOP")
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)
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)
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fsm.act("STOP",
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master.stop.eq(1),
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If(master.idle,
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If(~master.ack, self.nack.eq(1)),
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NextState("IDLE")
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)
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)
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self.comb += self.busy.eq(~fsm.ongoing("IDLE"))
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class Si549(Module, AutoCSR):
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def __init__(self, pads):
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