forked from M-Labs/artiq
drtio/gth_ultrascale: fix rtiox clock domain
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@ -672,7 +672,7 @@ class GTH(Module, TransceiverInterface):
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self.submodules.tx_phase_alignment = GTHTXPhaseAlignement(self.gths)
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TransceiverInterface.__init__(self, channel_interfaces)
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self.cd_rtiox = ClockDomain(reset_less=True)
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self.clock_domains.cd_rtiox = ClockDomain(reset_less=True)
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if create_buf:
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# GTH PLLs recover on their own from an interrupted clock input,
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# but be paranoid about HMC7043 noise.
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