forked from M-Labs/artiq
wrpll: more careful I2C timing
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parent
105dd60c78
commit
50302d57c0
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@ -49,8 +49,6 @@ class I2CMasterMachine(Module):
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self.ready.eq(1),
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If(self.start,
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NextState("START0"),
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).Elif(self.stop & self.start,
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NextState("RESTART0"),
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).Elif(self.stop,
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NextState("STOP0"),
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).Elif(self.write,
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@ -62,40 +60,44 @@ class I2CMasterMachine(Module):
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fsm.act("START0",
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NextValue(self.scl, 1),
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NextState("START1"))
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NextState("START1")
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)
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fsm.act("START1",
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NextValue(self.sda_o, 0),
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NextState("IDLE"))
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fsm.act("RESTART0",
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NextValue(self.scl, 0),
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NextState("RESTART1"))
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fsm.act("RESTART1",
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NextValue(self.sda_o, 1),
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NextState("START0"))
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NextState("IDLE")
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)
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fsm.act("STOP0",
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NextValue(self.scl, 0),
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NextState("STOP1"))
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NextState("STOP1")
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)
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fsm.act("STOP1",
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NextValue(self.scl, 1),
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NextValue(self.sda_o, 0),
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NextState("STOP2"))
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NextState("STOP2")
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)
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fsm.act("STOP2",
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NextValue(self.scl, 1),
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NextState("STOP3")
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)
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fsm.act("STOP3",
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NextValue(self.sda_o, 1),
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NextState("IDLE"))
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NextState("IDLE")
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)
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fsm.act("WRITE0",
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NextValue(self.scl, 0),
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NextState("WRITE1")
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)
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fsm.act("WRITE1",
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If(bits == 0,
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NextValue(self.sda_o, 1),
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NextState("READACK0"),
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).Else(
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NextValue(self.sda_o, data[7]),
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NextState("WRITE1"),
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NextState("WRITE2"),
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)
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)
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fsm.act("WRITE1",
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fsm.act("WRITE2",
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NextValue(self.scl, 1),
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NextValue(data[1:], data[:-1]),
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NextValue(bits, bits - 1),
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@ -240,6 +242,8 @@ def simulate_programmer():
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yield
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while (yield dut.busy):
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yield
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for _ in range(20):
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yield
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run_simulation(dut, generator(), vcd_name="tb.vcd")
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