forked from M-Labs/artiq
sayma_amc: fix RTIO TSC instantiation
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parent
6e43c41103
commit
66b3132c28
@ -287,7 +287,7 @@ class MasterDAC(MiniSoC, AMPSoC, RTMCommon):
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rtio_clk_freq=rtio_clk_freq)
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self.csr_devices.append("drtio_transceiver")
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self.rtio_tsc = rtio.TSC("async", glbl_fine_ts_width=3)
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self.submodules.rtio_tsc = rtio.TSC("async", glbl_fine_ts_width=3)
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drtio_csr_group = []
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drtioaux_csr_group = []
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@ -452,7 +452,7 @@ class Master(MiniSoC, AMPSoC):
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rtio_clk_freq=rtio_clk_freq)
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self.csr_devices.append("drtio_transceiver")
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self.rtio_tsc = rtio.TSC("async", glbl_fine_ts_width=3)
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self.submodules.rtio_tsc = rtio.TSC("async", glbl_fine_ts_width=3)
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drtio_csr_group = []
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drtioaux_csr_group = []
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@ -623,7 +623,7 @@ class Satellite(BaseSoC, RTMCommon):
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rtio_clk_freq=rtio_clk_freq)
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self.csr_devices.append("drtio_transceiver")
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self.rtio_tsc = rtio.TSC("sync", glbl_fine_ts_width=3)
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self.submodules.rtio_tsc = rtio.TSC("sync", glbl_fine_ts_width=3)
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rx0 = ClockDomainsRenamer({"rtio_rx": "rtio_rx0"})
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self.submodules.rx_synchronizer = rx0(XilinxRXSynchronizer())
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