forked from M-Labs/artiq
sayma_rtm_drtio: support v2 hardware
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parent
c7205ad82f
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@ -11,7 +11,7 @@ from migen.genlib.cdc import MultiReg
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from misoc.interconnect.csr import *
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from misoc.cores import gpio
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from misoc.cores.a7_gtp import *
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from misoc.targets.sayma_rtm import BaseSoC
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from misoc.targets.sayma_rtm import BaseSoC, soc_sayma_rtm_args, soc_sayma_rtm_argdict
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from misoc.integration.builder import Builder, builder_args, builder_argdict
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from artiq.gateware import rtio
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@ -96,9 +96,15 @@ class _SatelliteBase(BaseSoC):
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qpll = QPLL(si5324_clkout_buf, qpll_drtio_settings)
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self.submodules += qpll
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if self.hw_rev == "v1.0":
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drtio_data_pads = platform.request("sata", 0)
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elif self.hw_rev == "v2.0":
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drtio_data_pads = platform.request("rtm_amc_link", 0)
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else:
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raise NotImplementedError
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self.submodules.drtio_transceiver = gtp_7series.GTP(
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qpll_channel=qpll.channels[0],
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data_pads=[platform.request("sata", 0)],
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data_pads=[drtio_data_pads],
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sys_clk_freq=self.clk_freq,
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rtio_clk_freq=rtio_clk_freq)
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self.csr_devices.append("drtio_transceiver")
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@ -205,12 +211,13 @@ class SatmanSoCBuilder(Builder):
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def main():
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parser = argparse.ArgumentParser(
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description="ARTIQ device binary builder for Kasli systems")
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description="Sayma RTM gateware and firmware builder")
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builder_args(parser)
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soc_sayma_rtm_args(parser)
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parser.set_defaults(output_dir="artiq_sayma_rtm")
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args = parser.parse_args()
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soc = Satellite()
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soc = Satellite(**soc_sayma_rtm_argdict(args))
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builder = SatmanSoCBuilder(soc, **builder_argdict(args))
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try:
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builder.build()
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