forked from M-Labs/artiq
parent
9cf88329b2
commit
469a66db61
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@ -257,6 +257,10 @@ fn async_error_thread(io: Io) {
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}
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pub fn startup(io: &Io) {
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// The RTIO CRG may depend on the DRTIO transceiver clock.
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// Initialize DRTIO first to bring up transceiver clocking.
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drtio::startup(io);
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#[cfg(has_rtio_crg)]
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{
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#[cfg(has_rtio_clock_switch)]
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@ -296,7 +300,6 @@ pub fn startup(io: &Io) {
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}
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}
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drtio::startup(io);
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init_core(true);
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io.spawn(4096, async_error_thread);
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}
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@ -229,6 +229,23 @@ fn process_errors() {
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}
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}
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#[cfg(has_rtio_crg)]
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fn init_rtio_crg() {
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unsafe {
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csr::rtio_crg::pll_reset_write(0);
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}
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clock::spin_us(150);
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let locked = unsafe { csr::rtio_crg::pll_locked_read() != 0 };
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if !locked {
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error!("RTIO clock failed");
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}
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}
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#[cfg(not(has_rtio_crg))]
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fn init_rtio_crg() { }
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#[cfg(rtio_frequency = "150.0")]
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const SI5324_SETTINGS: si5324::FrequencySettings
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= si5324::FrequencySettings {
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@ -285,6 +302,7 @@ pub extern fn main() -> i32 {
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unsafe {
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csr::drtio_transceiver::stable_clkin_write(1);
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}
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init_rtio_crg();
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#[cfg(has_allaki_atts)]
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board_artiq::hmc542::program_all(8/*=4dB*/);
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@ -676,19 +676,23 @@ class Tester(_StandaloneBase):
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self.rtio_crg.cd_rtio.clk, self.grabber0.deserializer.cd_cl.clk)
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class _RTIOClockMultiplier(Module):
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class _RTIOClockMultiplier(Module, AutoCSR):
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def __init__(self, rtio_clk_freq):
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self.pll_reset = CSRStorage(reset=1)
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self.pll_locked = CSRStatus()
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self.clock_domains.cd_rtiox4 = ClockDomain(reset_less=True)
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# See "Global Clock Network Deskew Using Two BUFGs" in ug472.
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clkfbout = Signal()
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clkfbin = Signal()
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rtiox4_clk = Signal()
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pll_locked = Signal()
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self.specials += [
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Instance("MMCME2_BASE",
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p_CLKIN1_PERIOD=1e9/rtio_clk_freq,
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i_CLKIN1=ClockSignal("rtio"),
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i_RST=ResetSignal("rtio"),
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i_RST=self.pll_reset.storage,
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o_LOCKED=pll_locked,
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p_CLKFBOUT_MULT_F=8.0, p_DIVCLK_DIVIDE=1,
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@ -697,7 +701,9 @@ class _RTIOClockMultiplier(Module):
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p_CLKOUT0_DIVIDE_F=2.0, o_CLKOUT0=rtiox4_clk,
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),
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Instance("BUFG", i_I=clkfbout, o_O=clkfbin),
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Instance("BUFG", i_I=rtiox4_clk, o_O=self.cd_rtiox4.clk)
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Instance("BUFG", i_I=rtiox4_clk, o_O=self.cd_rtiox4.clk),
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MultiReg(pll_locked, self.pll_locked.status)
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]
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@ -781,7 +787,8 @@ class _MasterBase(MiniSoC, AMPSoC):
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platform.add_false_path_constraints(
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self.crg.cd_sys.clk, gtp.rxoutclk)
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self.submodules.rtio_clkmul = _RTIOClockMultiplier(rtio_clk_freq)
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self.submodules.rtio_crg = _RTIOClockMultiplier(rtio_clk_freq)
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self.csr_devices.append("rtio_crg")
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fix_serdes_timing_path(platform)
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def add_rtio(self, rtio_channels):
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@ -906,7 +913,8 @@ class _SatelliteBase(BaseSoC):
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self.crg.cd_sys.clk,
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gtp.txoutclk, gtp.rxoutclk)
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self.submodules.rtio_clkmul = _RTIOClockMultiplier(rtio_clk_freq)
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self.submodules.rtio_crg = _RTIOClockMultiplier(rtio_clk_freq)
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self.csr_devices.append("rtio_crg")
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fix_serdes_timing_path(platform)
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def add_rtio(self, rtio_channels):
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