forked from M-Labs/artiq
wrpll/thls: simple simulation demo
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@ -1,6 +1,10 @@
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import inspect
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import ast
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from copy import copy
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import operator
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from functools import reduce
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from migen import *
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class Isn:
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@ -40,17 +44,14 @@ class SubIsn(Isn):
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class MulIsn(Isn):
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opcode = 3
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class ShiftIsn(Isn):
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class CopyIsn(Isn):
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opcode = 4
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class CopyIsn(Isn):
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class InputIsn(Isn):
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opcode = 5
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class InputIsn(Isn):
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opcode = 6
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class OutputIsn(Isn):
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opcode = 7
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opcode = 6
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class ASTCompiler:
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@ -132,7 +133,6 @@ class Processor:
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AddIsn: 2,
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SubIsn: 2,
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MulIsn: 1 + self.multiplier_stages,
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ShiftIsn: 2,
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CopyIsn: 1,
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InputIsn: 1
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}[isn.__class__]
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@ -160,6 +160,12 @@ class Processor:
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r |= value
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return r
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def instruction_bits(self):
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return 3*self.reg_bits + self.opcode_bits
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def implement(self, program, data):
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return ProcessorImpl(self, program, data)
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class Scheduler:
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def __init__(self, processor, reserved_data, program):
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@ -292,14 +298,167 @@ def compile(processor, function):
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scheduler = Scheduler(processor, len(astcompiler.data), astcompiler.program)
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scheduler.schedule()
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max_reg = max(max(max(isn.inputs + [0]) for isn in scheduler.output), max(v[1] for k, v in scheduler.exits.items()))
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return CompiledProgram(
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processor=processor,
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program=scheduler.output,
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exits={k: v[1] for k,v in scheduler.exits.items()},
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data=astcompiler.data,
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exits={k: v[1] for k, v in scheduler.exits.items()},
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data=astcompiler.data + [0]*(max_reg - len(astcompiler.data) + 1),
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glbs=astcompiler.globals)
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class BaseUnit(Module):
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def __init__(self, data_width):
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self.stb_i = Signal()
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self.i0 = Signal(data_width)
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self.i1 = Signal(data_width)
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self.stb_o = Signal()
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self.o = Signal(data_width)
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class NopUnit(BaseUnit):
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pass
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class OpUnit(BaseUnit):
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def __init__(self, op, data_width, stages):
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BaseUnit.__init__(self, data_width)
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o = op(self.i0, self.i1)
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stb_o = self.stb_i
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for i in range(stages):
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n_o = Signal(data_width)
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n_stb_o = Signal()
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self.sync += [
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n_o.eq(o),
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n_stb_o.eq(stb_o)
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]
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o = n_o
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stb_o = n_stb_o
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self.comb += [
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self.o.eq(o),
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self.stb_o.eq(stb_o)
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]
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class CopyUnit(BaseUnit):
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def __init__(self, data_width):
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BaseUnit.__init__(self, data_width)
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self.comb += [
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self.stb_o.eq(self.stb_i),
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self.o.eq(self.i0)
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]
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class InputUnit(BaseUnit):
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def __init__(self, data_width, input_stb, input):
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BaseUnit.__init__(self, data_width)
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# TODO
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self.comb += [
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self.stb_o.eq(self.stb_i),
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self.o.eq(42)
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]
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class OutputUnit(BaseUnit):
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def __init__(self, data_width, output_stb, output):
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BaseUnit.__init__(self, data_width)
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self.sync += [
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output_stb.eq(self.stb_i),
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output.eq(self.i0)
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]
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class ProcessorImpl(Module):
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def __init__(self, pd, program, data):
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self.input_stb = Signal()
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self.input = Signal(pd.data_width)
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self.output_stb = Signal()
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self.output = Signal(pd.data_width)
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# # #
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program_mem = Memory(pd.instruction_bits(), pd.program_rom_size, init=program)
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data_mem0 = Memory(pd.data_width, pd.data_ram_size, init=data)
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data_mem1 = Memory(pd.data_width, pd.data_ram_size, init=data)
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self.specials += program_mem, data_mem0, data_mem1
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pc = Signal(pd.instruction_bits())
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pc_next = Signal.like(pc)
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pc_en = Signal()
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self.sync += pc.eq(pc_next)
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self.comb += [
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If(pc_en,
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pc_next.eq(pc + 1)
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).Else(
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pc_next.eq(0)
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)
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]
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program_mem_port = program_mem.get_port()
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self.specials += program_mem_port
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self.comb += program_mem_port.adr.eq(pc_next)
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# TODO
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self.comb += pc_en.eq(1)
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s = 0
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opcode = Signal(pd.opcode_bits)
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self.comb += opcode.eq(program_mem_port.dat_r[s:s+pd.opcode_bits])
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s += pd.opcode_bits
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r0 = Signal(pd.reg_bits)
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self.comb += r0.eq(program_mem_port.dat_r[s:s+pd.reg_bits])
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s += pd.reg_bits
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r1 = Signal(pd.reg_bits)
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self.comb += r1.eq(program_mem_port.dat_r[s:s+pd.reg_bits])
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s += pd.reg_bits
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exit = Signal(pd.reg_bits)
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self.comb += exit.eq(program_mem_port.dat_r[s:s+pd.reg_bits])
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data_read_port0 = data_mem0.get_port()
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data_read_port1 = data_mem1.get_port()
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self.specials += data_read_port0, data_read_port1
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self.comb += [
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data_read_port0.adr.eq(r0),
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data_read_port1.adr.eq(r1)
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]
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data_write_port = data_mem0.get_port(write_capable=True)
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data_write_port_dup = data_mem1.get_port(write_capable=True)
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self.specials += data_write_port, data_write_port_dup
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self.comb += [
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data_write_port_dup.we.eq(data_write_port.we),
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data_write_port_dup.adr.eq(data_write_port.adr),
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data_write_port_dup.dat_w.eq(data_write_port.dat_w),
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data_write_port.adr.eq(exit)
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]
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nop = NopUnit(pd.data_width)
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adder = OpUnit(operator.add, pd.data_width, 1)
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subtractor = OpUnit(operator.sub, pd.data_width, 1)
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multiplier = OpUnit(operator.mul, pd.data_width, pd.multiplier_stages)
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copier = CopyUnit(pd.data_width)
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inu = InputUnit(pd.data_width, self.input_stb, self.input)
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outu = OutputUnit(pd.data_width, self.output_stb, self.output)
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units = [nop, adder, subtractor, multiplier, copier, inu, outu]
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self.submodules += units
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for n, unit in enumerate(units):
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self.sync += unit.stb_i.eq(opcode == n)
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self.comb += [
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unit.i0.eq(data_read_port0.dat_r),
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unit.i1.eq(data_read_port1.dat_r),
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If(unit.stb_o,
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data_write_port.we.eq(1),
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data_write_port.dat_w.eq(unit.o)
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)
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]
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a = 0
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b = 0
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c = 0
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@ -312,7 +471,22 @@ def foo(x):
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return 4748*a + 259*b - 155*c
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cp = compile(Processor(), foo)
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cp.pretty_print()
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cp.dimension_memories()
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print(cp.encode())
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def simple_test(x):
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a = 5 + 3
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return a*4
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if __name__ == "__main__":
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proc = Processor()
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cp = compile(proc, simple_test)
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cp.pretty_print()
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cp.dimension_memories()
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print(cp.encode())
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proc_impl = proc.implement(cp.encode(), cp.data)
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def wait_result():
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while not (yield proc_impl.output_stb):
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yield
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result = yield proc_impl.output
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print(result)
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run_simulation(proc_impl, [wait_result()], vcd_name="test.vcd")
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