forked from M-Labs/artiq
metlino: drive clock muxes
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@ -53,6 +53,8 @@ class Master(MiniSoC, AMPSoC):
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platform = self.platform
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rtio_clk_freq = 150e6
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self.comb += platform.request("input_clk_sel").eq(1)
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self.comb += platform.request("filtered_clk_sel").eq(1)
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self.submodules.si5324_rst_n = gpio.GPIOOut(platform.request("si5324").rst_n)
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self.csr_devices.append("si5324_rst_n")
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i2c = self.platform.request("i2c")
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