forked from M-Labs/artiq
sayma: drive filtered_clk_sel on master variant
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@ -388,6 +388,7 @@ class Master(MiniSoC, AMPSoC):
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self.config["SI5324_AS_SYNTHESIZER"] = None
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self.config["RTIO_FREQUENCY"] = str(rtio_clk_freq/1e6)
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self.comb += platform.request("filtered_clk_sel").eq(1)
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self.comb += platform.request("sfp_tx_disable", 0).eq(0)
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self.submodules.drtio_transceiver = gth_ultrascale.GTH(
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clock_pads=platform.request("cdr_clk_clean", 0),
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