forked from M-Labs/artiq
wrpll: share DDMTD counter
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05c5fed07d
commit
7098854b0f
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@ -21,5 +21,7 @@ class WRPLL(Module, AutoCSR):
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self.submodules.main_dcxo = Si549(main_dcxo_i2c)
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self.submodules.helper_dcxo = Si549(helper_dxco_i2c)
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self.submodules.ddmtd_helper = DDMTD(N, ddmtd_inputs.rec_clk)
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self.submodules.ddmtd_main = DDMTD(N, ddmtd_inputs.main_xo)
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ddmtd_counter = Signal(N)
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self.sync.helper += ddmtd_counter.eq(ddmtd_counter + 1)
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self.submodules.ddmtd_helper = DDMTD(ddmtd_counter, ddmtd_inputs.rec_clk)
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self.submodules.ddmtd_main = DDMTD(ddmtd_counter, ddmtd_inputs.main_xo)
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@ -4,13 +4,13 @@ from misoc.interconnect.csr import *
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class DDMTDEdgeDetector(Module):
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def __init__(self, i):
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def __init__(self, input_signal):
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self.rising = Signal()
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history = Signal(4)
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deglitched = Signal()
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self.sync.helper += history.eq(Cat(history[1:], i))
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self.comb += deglitched.eq(i | history[0] | history[1] | history[2] | history[3])
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self.sync.helper += history.eq(Cat(history[1:], input_signal))
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self.comb += deglitched.eq(input_signal | history[0] | history[1] | history[2] | history[3])
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deglitched_r = Signal()
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self.sync.helper += [
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@ -20,22 +20,20 @@ class DDMTDEdgeDetector(Module):
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class DDMTD(Module, AutoCSR):
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def __init__(self, N, i):
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def __init__(self, counter, input_signal):
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self.arm = CSR()
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self.tag = CSRStatus(N)
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self.tag = CSRStatus(len(counter))
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# in helper clock domain
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self.h_tag = Signal(N)
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self.h_tag = Signal(len(counter))
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self.h_tag_update = Signal()
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# # #
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ed = DDMTDEdgeDetector(i)
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ed = DDMTDEdgeDetector(input_signal)
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self.submodules += ed
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counter = Signal(N)
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self.sync.helper += [
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counter.eq(counter + 1),
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self.h_tag_update.eq(0),
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If(ed.rising,
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self.h_tag_update.eq(1),
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@ -49,7 +47,7 @@ class DDMTD(Module, AutoCSR):
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tag_update = Signal()
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self.sync += tag_update.eq(tag_update_ps.o)
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tag = Signal(N)
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tag = Signal(len(counter))
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self.h_tag.attr.add("no_retiming")
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self.specials += MultiReg(self.h_tag, tag)
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