forked from M-Labs/artiq
wrpll: implement filters and connect to Si549
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@ -5,6 +5,7 @@ from misoc.interconnect.csr import *
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from artiq.gateware.drtio.wrpll.si549 import Si549
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from artiq.gateware.drtio.wrpll.ddmtd import DDMTD
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from artiq.gateware.drtio.wrpll import thls, filters
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class FrequencyCounter(Module, AutoCSR):
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@ -48,12 +49,22 @@ class WRPLL(Module, AutoCSR):
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AsyncResetSynchronizer(self.cd_helper, self.helper_reset.storage)
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]
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self.submodules.main_dcxo = Si549(main_dcxo_i2c)
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self.submodules.helper_dcxo = Si549(helper_dxco_i2c)
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self.submodules.main_dcxo = Si549(main_dcxo_i2c)
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self.submodules.helper_frequency = FrequencyCounter()
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self.submodules.helper_frequency = FrequencyCounter() # for diagnostics
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ddmtd_counter = Signal(N)
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self.sync.helper += ddmtd_counter.eq(ddmtd_counter + 1)
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self.submodules.ddmtd_helper = DDMTD(ddmtd_counter, ddmtd_inputs.rec_clk)
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self.submodules.ddmtd_main = DDMTD(ddmtd_counter, ddmtd_inputs.main_xo)
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helper_cd = ClockDomainsRenamer("helper")
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self.submodules.filter_helper = helper_cd(thls.make(filters.helper, data_width=48))
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self.submodules.filter_main = helper_cd(thls.make(filters.main, data_width=48))
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self.comb += [
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self.helper_dcxo.adpll_stb.eq(self.filter_helper.output_stb),
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self.helper_dcxo.adpll.eq(self.filter_helper.output),
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self.main_dcxo.adpll_stb.eq(self.filter_main.output_stb),
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self.main_dcxo.adpll.eq(self.filter_main.output)
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]
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@ -589,6 +589,13 @@ class ProcessorImpl(Module):
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)
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def make(function, **kwargs):
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proc = Processor(**kwargs)
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cp = compile(proc, simple_test)
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cp.dimension_processor()
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return proc.implement(cp.encode(), cp.data)
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a = 0
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b = 0
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c = 0
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