forked from M-Labs/artiq
sayma_rtm_drtio: cleanup (v2.0 only)
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5612b31860
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4198033657
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@ -97,15 +97,9 @@ class _SatelliteBase(BaseSoC):
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qpll = QPLL(si5324_clkout_buf, qpll_drtio_settings)
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self.submodules += qpll
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if self.hw_rev == "v1.0":
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drtio_data_pads = platform.request("sata", 0)
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elif self.hw_rev == "v2.0":
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drtio_data_pads = platform.request("rtm_amc_link", 0)
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else:
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raise NotImplementedError
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self.submodules.drtio_transceiver = gtp_7series.GTP(
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qpll_channel=qpll.channels[0],
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data_pads=[drtio_data_pads],
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data_pads=[platform.request("rtm_amc_link", 0)],
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sys_clk_freq=self.clk_freq,
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rtio_clk_freq=rtio_clk_freq)
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self.csr_devices.append("drtio_transceiver")
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@ -137,8 +131,7 @@ class _SatelliteBase(BaseSoC):
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self.add_memory_group("drtioaux_mem", ["drtioaux0_mem"])
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self.config["RTIO_FREQUENCY"] = str(rtio_clk_freq/1e6)
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if self.hw_rev == "v2.0":
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self.comb += platform.request("filtered_clk_sel").eq(1)
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self.comb += platform.request("filtered_clk_sel").eq(1)
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self.submodules.siphaser = SiPhaser7Series(
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si5324_clkin=platform.request("si5324_clkin"),
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rx_synchronizer=self.rx_synchronizer,
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@ -167,9 +160,10 @@ class _SatelliteBase(BaseSoC):
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fix_serdes_timing_path(platform)
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# HMC clock chip and DAC control
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self.comb += platform.request("ad9154_rst_n", 0).eq(1)
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if self.hw_rev == "v2.0":
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self.comb += platform.request("ad9154_rst_n", 1).eq(1)
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self.comb += [
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platform.request("ad9154_rst_n", 0).eq(1),
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platform.request("ad9154_rst_n", 1).eq(1)
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]
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self.submodules.converter_spi = spi2.SPIMaster(spi2.SPIInterface(
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platform.request("hmc_spi"),
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platform.request("ad9154_spi", 0),
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@ -181,16 +175,17 @@ class _SatelliteBase(BaseSoC):
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self.submodules.hmc7043_gpo = gpio.GPIOIn(
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platform.request("hmc7043_gpo"))
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self.csr_devices.append("hmc7043_gpo")
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if self.hw_rev == "v2.0":
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self.comb += platform.request("hmc830_pwr_en").eq(1)
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self.submodules.hmc7043_out_en = gpio.GPIOOut(
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platform.request("hmc7043_out_en"))
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self.csr_devices.append("hmc7043_out_en")
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self.config["HAS_HMC830_7043"] = None
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self.config["CONVERTER_SPI_HMC830_CS"] = 0
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self.config["CONVERTER_SPI_HMC7043_CS"] = 1
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self.config["HMC830_REF"] = "150"
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# HMC workarounds
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self.comb += platform.request("hmc830_pwr_en").eq(1)
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self.submodules.hmc7043_out_en = gpio.GPIOOut(
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platform.request("hmc7043_out_en"))
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self.csr_devices.append("hmc7043_out_en")
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def add_rtio(self, rtio_channels):
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self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)
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self.csr_devices.append("rtio_moninj")
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