forked from M-Labs/artiq
wrpll: update OBUFDS_GTE2 comment
Seems O can fan out simultaneously to transceiver and fabric. Kasli is using ODIV2 for no particular reason.
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@ -27,12 +27,9 @@ class DDMTDSamplerGTP(Module):
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self.rec_clk = Signal()
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self.main_xo = Signal()
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# Getting the main XO signal from IBUFDS_GTE2 is problematic because:
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# 1. the clock gets divided by 2
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# 2. the transceiver PLL craps out if an improper clock signal is applied,
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# Getting the main XO signal from IBUFDS_GTE2 is problematic because
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# the transceiver PLL craps out if an improper clock signal is applied,
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# so we are disabling the buffer until the clock is stable.
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# 3. UG482 says "The O and ODIV2 outputs are not phase matched to each other",
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# which may or may not be a problem depending on what it actually means.
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main_xo_se = Signal()
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self.specials += [
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Instance("IBUFDS",
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