forked from M-Labs/artiq
sayma_rtm: drive clk_src_ext_sel
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@ -205,6 +205,8 @@ class Satellite(_SatelliteBase):
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self.add_rtio(rtio_channels)
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self.comb += platform.request("clk_src_ext_sel").eq(0)
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# HMC clock chip and DAC control
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self.comb += [
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platform.request("ad9154_rst_n", 0).eq(1),
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