forked from M-Labs/artiq
wrpll: constrain clocks
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05e2e1899a
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2b5213b013
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@ -129,6 +129,7 @@ class SatelliteBase(MiniSoC):
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self.add_memory_group("drtioaux_mem", drtioaux_memory_group)
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self.add_csr_group("drtiorep", drtiorep_csr_group)
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rtio_clk_period = 1e9/rtio_clk_freq
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self.config["RTIO_FREQUENCY"] = str(rtio_clk_freq/1e6)
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if with_wrpll:
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self.comb += [
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@ -144,6 +145,8 @@ class SatelliteBase(MiniSoC):
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helper_dxco_i2c=platform.request("ddmtd_helper_dcxo_i2c"),
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ddmtd_inputs=self.wrpll_sampler)
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self.csr_devices.append("wrpll")
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platform.add_period_constraint(self.wrpll.cd_helper.clk, rtio_clk_period*0.99)
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platform.add_false_path_constraints(self.crg.cd_sys.clk, self.wrpll.cd_helper.clk)
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else:
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self.comb += platform.request("filtered_clk_sel").eq(1)
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self.submodules.siphaser = SiPhaser7Series(
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@ -162,7 +165,6 @@ class SatelliteBase(MiniSoC):
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self.config["I2C_BUS_COUNT"] = 1
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self.config["HAS_SI5324"] = None
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rtio_clk_period = 1e9/rtio_clk_freq
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gth = self.drtio_transceiver.gths[0]
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platform.add_period_constraint(gth.txoutclk, rtio_clk_period/2)
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platform.add_period_constraint(gth.rxoutclk, rtio_clk_period)
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@ -132,6 +132,8 @@ class _SatelliteBase(BaseSoC):
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self.add_csr_group("drtioaux", ["drtioaux0"])
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self.add_memory_group("drtioaux_mem", ["drtioaux0_mem"])
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gtp = self.drtio_transceiver.gtps[0]
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rtio_clk_period = 1e9/rtio_clk_freq
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self.config["RTIO_FREQUENCY"] = str(rtio_clk_freq/1e6)
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if with_wrpll:
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self.comb += [
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@ -148,6 +150,9 @@ class _SatelliteBase(BaseSoC):
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helper_dxco_i2c=platform.request("ddmtd_helper_dcxo_i2c"),
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ddmtd_inputs=self.wrpll_sampler)
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self.csr_devices.append("wrpll")
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platform.add_period_constraint(self.wrpll.cd_helper.clk, rtio_clk_period*0.99)
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platform.add_false_path_constraints(self.crg.cd_sys.clk, self.wrpll.cd_helper.clk)
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platform.add_false_path_constraints(self.wrpll.cd_helper.clk, gtp.rxoutclk)
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else:
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self.comb += platform.request("filtered_clk_sel").eq(1)
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self.submodules.siphaser = SiPhaser7Series(
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@ -165,8 +170,6 @@ class _SatelliteBase(BaseSoC):
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self.config["HAS_SI5324"] = None
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self.config["SI5324_SOFT_RESET"] = None
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rtio_clk_period = 1e9/rtio_clk_freq
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gtp = self.drtio_transceiver.gtps[0]
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platform.add_period_constraint(gtp.txoutclk, rtio_clk_period)
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platform.add_period_constraint(gtp.rxoutclk, rtio_clk_period)
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platform.add_false_path_constraints(
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