forked from M-Labs/artiq
sayma_amc: enable DRTIO on master SATA connector for MasterDAC variant
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e85df13127
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@ -279,7 +279,7 @@ class MasterDAC(MiniSoC, AMPSoC, RTMCommon):
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]
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self.submodules.drtio_transceiver = gth_ultrascale.GTH(
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clock_pads=self.ad9154_crg.refclk,
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data_pads=[platform.request("sfp", i) for i in range(2)],
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data_pads=[platform.request("sata")] + [platform.request("sfp", i) for i in range(2)],
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sys_clk_freq=self.clk_freq,
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rtio_clk_freq=rtio_clk_freq)
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self.csr_devices.append("drtio_transceiver")
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@ -290,7 +290,7 @@ class MasterDAC(MiniSoC, AMPSoC, RTMCommon):
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drtioaux_csr_group = []
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drtioaux_memory_group = []
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drtio_cri = []
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for i in range(2):
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for i in range(3):
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core_name = "drtio" + str(i)
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coreaux_name = "drtioaux" + str(i)
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memory_name = "drtioaux" + str(i) + "_mem"
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