forked from M-Labs/artiq
wrpll: encode thls program
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5f461d08cd
commit
34222b3f38
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@ -29,35 +29,28 @@ class Isn:
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class NopIsn(Isn):
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pass
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opcode = 0
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class AddIsn(Isn):
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pass
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opcode = 1
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class SubIsn(Isn):
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pass
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opcode = 2
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class MulIsn(Isn):
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pass
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opcode = 3
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class ShiftIsn(Isn):
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pass
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opcode = 4
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class CopyIsn(Isn):
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pass
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opcode = 5
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class InputIsn(Isn):
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pass
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opcode = 6
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class OutputIsn(Isn):
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pass
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opcode = 7
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class ASTCompiler:
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@ -126,8 +119,13 @@ class ASTCompiler:
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class Processor:
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def __init__(self, multiplier_stages=2):
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def __init__(self, data_width=32, multiplier_stages=2):
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self.data_width = data_width
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self.multiplier_stages = multiplier_stages
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self.program_rom_size = None
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self.data_ram_size = None
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self.opcode_bits = 3
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self.reg_bits = None
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def get_instruction_latency(self, isn):
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return {
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@ -139,6 +137,29 @@ class Processor:
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InputIsn: 1
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}[isn.__class__]
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def encode_instruction(self, isn, exit):
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opcode = isn.opcode
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if isn.immediate is not None:
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r0 = isn.immediate
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if len(isn.inputs) >= 1:
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r1 = isn.inputs[0]
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else:
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r1 = 0
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else:
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if len(isn.inputs) >= 1:
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r0 = isn.inputs[0]
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else:
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r0 = 0
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if len(isn.inputs) >= 2:
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r1 = isn.inputs[1]
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else:
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r1 = 0
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r = 0
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for value, bits in ((exit, self.reg_bits), (r1, self.reg_bits), (r0, self.reg_bits), (opcode, self.opcode_bits)):
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r <<= bits
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r |= value
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return r
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class Scheduler:
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def __init__(self, processor, reserved_data, program):
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@ -218,15 +239,36 @@ class Scheduler:
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self.output += [NopIsn()]*(max(self.exits.keys()) - len(self.output) + 1)
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return self.output
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class CompiledProgram:
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def __init__(self, processor, program, exits, data, glbs):
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self.processor = processor
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self.program = program
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self.exits = exits
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self.data = data
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self.globals = glbs
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def pretty_print(self):
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for cycle, isn in enumerate(self.output):
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for cycle, isn in enumerate(self.program):
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l = "{:4d} {:15}".format(cycle, str(isn))
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if cycle in self.exits:
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l += " -> r{}".format(self.exits[cycle][1])
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l += " -> r{}".format(self.exits[cycle])
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print(l)
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def dimension_memories(self):
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self.processor.program_rom_size = len(self.program)
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self.processor.data_ram_size = len(self.data)
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self.processor.reg_bits = (self.processor.data_ram_size - 1).bit_length()
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def compile(function):
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def encode(self):
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r = []
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for i, isn in enumerate(self.program):
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exit = self.exits.get(i, 0)
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r.append(self.processor.encode_instruction(isn, exit))
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return r
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def compile(processor, function):
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node = ast.parse(inspect.getsource(function))
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assert isinstance(node, ast.Module)
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assert len(node.body) == 1
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@ -244,12 +286,16 @@ def compile(function):
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arg_r = astcompiler.input(arg)
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for node in body:
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astcompiler.emit(node)
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print(astcompiler.data)
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print(astcompiler.program)
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scheduler = Scheduler(Processor(), len(astcompiler.data), astcompiler.program)
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scheduler = Scheduler(processor, len(astcompiler.data), astcompiler.program)
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scheduler.schedule()
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scheduler.pretty_print()
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return CompiledProgram(
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processor=processor,
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program=scheduler.output,
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exits={k: v[1] for k,v in scheduler.exits.items()},
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data=astcompiler.data,
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glbs=astcompiler.globals)
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a = 0
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@ -264,4 +310,7 @@ def foo(x):
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return 4748*a + 259*b - 155*c
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compile(foo)
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cp = compile(Processor(), foo)
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cp.pretty_print()
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cp.dimension_memories()
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print(cp.encode())
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