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8,485 Commits 63 Branches 34 Tags 19 MiB
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1593 Commits

Author SHA1 Message Date
occheung 838cc80922
EFC: Implement OOB reset 2023-09-03 10:25:08 +08:00
occheung df99450faa
shuttler: add pdq-based waveform generator 2023-08-30 23:38:39 +08:00
linuswck ddb2b5e3a1 efc: add shuttler DAC parallel data interface pads 2023-08-30 10:25:39 +08:00
linuswck b56f7e429a
drtio: rename drtio_transceiver to gt_drtio 2023-08-28 04:50:46 +00:00
Sebastien Bourdeauducq 3452d0c423 efc: use variant (expected everywhere else) 2023-08-25 15:52:40 +08:00
Sebastien Bourdeauducq f5cbca9c29 kasli: implement DRTIO-over-EEM 2023-08-25 12:47:33 +08:00
linuswck 737ff79ae7 eem: add efc 2023-08-25 12:01:17 +08:00
linuswck dc97d3aee6 drtio-eem: CONFIG_EEM_TRANSCEIVERS -> CONFIG_EEM_DRTIO_COUNT 2023-08-25 11:49:39 +08:00
Sebastien Bourdeauducq 5d38db19d0 drtio-eem: remove unnecessary rtio_rx clock domain 2023-08-25 11:32:28 +08:00
linuswck cd22e42cb4
efc: add DRTIO virtual LEDs 
- EFC Gateware: Add virtual_leds to rtio
- EFC Firmware: io_expander is kept being serviced to update
  virtual_leds after init
 2023-08-23 06:21:14 +00:00
linuswck b7bac8c9d8 EFC: Add SPI Gateware for Shuttler DAC 
- Verified by a functional test reading back the rev register
 2023-08-23 09:04:16 +08:00
occheung 68dd0e029f targets: add efc target 2023-08-10 00:02:01 +00:00
occheung 64d3f867a0
add DRTIO-over-EEM PHY 
for EFC and perhaps Phaser
 2023-08-09 23:59:40 +00:00
Jonathan Coates 9a84575649
eem_7series: fix typo in 77293d5 
Signed-off-by: Jonathan Coates <jonathan.coates@oxionics.com>
 2023-07-11 23:09:15 +00:00
Sebastien Bourdeauducq 48bc8a2ecc gtx_7series_init: GTH -> GTX (NFC) 2023-07-10 11:26:07 +08:00
Denis Ovchinnikov 93882eb3ce kasli-soc: fix of SYS CLK switch failure 
Change initialization behaviour of GTX transceivers
--
Modify the config parms CPLL of GTX transceiver for PLL to lock correctly
Modify the enabling requirement of GTX input clock buffer IBUFDS_GTE2 so
    that it depends on GTX PLL locked signal instead of TX Init Done
Modify the GTX Init FSM so that BruteForceClock Aligner can reset GTX
    transceiver without resetting the GTX transceiver PLL

kasli-soc: fix of SYS CLK switch failure
Changed initialization of GTX transceivers.
Successful SYS CLK switching requires IBUFDS_GTE2 to be properly enabled and not disabled during GTX transceiver initialization.
For this reason, CPLL is not reset during GTX initialization and clock alignment.

kasli-soc: refractor fix of SYS CLK switch failure
Remove gtXxreset & cpllreset assertion and deassertion
The removed code does not affect the fix
 2023-07-10 03:24:28 +00:00
Sebastien Bourdeauducq 77293d53e3 json: use schema defaults when applicable 2023-06-16 16:59:08 +08:00
Sebastien Bourdeauducq a792bc5456 json: factor handling of deprecated 'base' 2023-06-16 16:32:42 +08:00
Sebastien Bourdeauducq 20d4712815 json: base -> drtio_role 2023-06-16 16:17:31 +08:00
Spaqin 82bd913f63
satellites: add kernel cpu 2023-06-16 15:44:31 +08:00
mwojcik 29cb7e785d fix missing DIFF_TERM for Sampler and Mirny inputs 2023-06-02 17:21:00 +08:00
Denis Ovchinnikov 22e2514ce6 update configuration of IBUFDS_GTE2 
Input clock is terminated internally with 50 Ohm on each leg and to 4/5 MGTAVCC.
 2023-05-30 11:42:51 +08:00
Sebastien Bourdeauducq 58cc3b8d0a kasli_generic: fix LooseVersion deprecation warning 2023-05-23 19:36:06 +08:00
Jonathan Coates ea9fe9b4e1
dma: fix off-by-one error in RawSlicer (#2090) 
Signed-off-by: Jonathan Coates <jonathan.coates@oxionics.com>
 2023-05-23 11:15:39 +08:00
mwojcik 0b03126038 satman: support analyzer packets 2023-05-19 11:39:14 +08:00
mwojcik c36b6b3b65 master: only local rtio events in analyzer 2023-05-19 11:39:14 +08:00
mwojcik c0ca27e6cf satellite: add rtio_analyzer, only for local rtio 2023-05-19 11:39:14 +08:00
mwojcik a533f2a0cd rtio: SED, InputCollector use rio clock domain 2023-04-28 17:49:12 +08:00
mwojcik 90a6fe1c35 satellite: add dma to gateware 2023-02-23 17:33:23 +08:00
mwojcik d0437f5672 rtio core: fix minimum_coarse_timestamp 2023-02-22 10:44:25 +08:00
Sebastien Bourdeauducq b8968262d7 Merge branch 'syncrtio' 2023-01-12 16:44:54 +08:00
Sebastien Bourdeauducq 514ac953ce remove obsolete SI5324_AS_SYNTHESIZER config option 2023-01-12 13:01:08 +08:00
mwojcik 70edc9c5c6 test_write_underflow: decrease underflow delay 2023-01-11 12:02:51 +08:00
mwojcik 9042426872 echo test: add two more yields 2023-01-11 12:02:51 +08:00
mwojcik cd860beda2 test_full_stack: restore missing check_ttls 2023-01-11 12:02:51 +08:00
mwojcik 627504b60e test_dma: remove redundant clock 2023-01-11 12:02:51 +08:00
mwojcik eb3742fb08 kc705: do not reset si5324 during clock switch 2023-01-09 18:18:21 +08:00
Sebastien Bourdeauducq 63f1a6d197 drtio: partially fix tests 2023-01-06 18:33:13 +08:00
Sebastien Bourdeauducq ec893222a4 rtio: remove support for async mode 2023-01-06 18:22:05 +08:00
Sebastien Bourdeauducq 573a895c1e remove RTIOClockMultiplier 2023-01-06 17:59:18 +08:00
Sebastien Bourdeauducq cf2a4972f7 remove WRPLL 2023-01-06 17:53:11 +08:00
Sebastien Bourdeauducq 5da9794895 remove Sayma and Metlino support 2023-01-06 17:41:12 +08:00
Spaqin 3838dfc1d1
DRTIO: RTIO/SYS clock merge, KC705 2023-01-06 07:13:38 +08:00
Spaqin 17efc28dbe
DRTIO: RTIO/SYS clock merge 2022-12-17 15:39:54 +08:00
mwojcik ad000609ce simplify tsc with no rtio/sys clk distinction 2022-11-01 08:12:54 +08:00
mwojcik f8eb695c0f dma test: no more rsys or rtio domains 2022-11-01 08:12:54 +08:00
mwojcik 458bd8a927 kasli_generic: remove rtio clockdomain reference 2022-11-01 08:12:54 +08:00
mwojcik a6856a5e4a rtio: remove rtio clock, use sys instead 2022-11-01 08:12:54 +08:00
mwojcik 1eb87164be kasli: remove rtiocrg, use rtio/sys merge 2022-11-01 08:12:54 +08:00
Robert Jördens 1820e1f715 phaser: cleanup 2022-10-19 16:25:33 +02:00