forked from M-Labs/artiq
drtio: 8-bit address
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8caea0e6d3
commit
f74dda639f
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@ -27,7 +27,7 @@ class RTPacketMaster(Module):
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self.sr_notwrite = Signal()
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self.sr_timestamp = Signal(64)
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self.sr_chan_sel = Signal(24)
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self.sr_address = Signal(16)
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self.sr_address = Signal(8)
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self.sr_data = Signal(512)
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# buffer space reply interface
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@ -85,12 +85,12 @@ class RTPacketMaster(Module):
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# Write FIFO and extra data count
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sr_fifo = ClockDomainsRenamer({"write": "sys", "read": "rtio"})(
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AsyncFIFO(1+64+24+16+512, sr_fifo_depth))
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AsyncFIFO(1+64+24+8+512, sr_fifo_depth))
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self.submodules += sr_fifo
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sr_notwrite_d = Signal()
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sr_timestamp_d = Signal(64)
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sr_chan_sel_d = Signal(24)
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sr_address_d = Signal(16)
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sr_address_d = Signal(8)
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sr_data_d = Signal(512)
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self.comb += [
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sr_fifo.we.eq(self.sr_stb),
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@ -115,7 +115,7 @@ class RTPacketMaster(Module):
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sr_notwrite = Signal()
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sr_timestamp = Signal(64)
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sr_chan_sel = Signal(24)
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sr_address = Signal(16)
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sr_address = Signal(8)
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sr_extra_data_cnt = Signal(8)
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sr_data = Signal(512)
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@ -58,7 +58,7 @@ class RTPacketRepeater(Module):
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cb0_cmd = Signal(2)
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cb0_timestamp = Signal(64)
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cb0_chan_sel = Signal(24)
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cb0_o_address = Signal(16)
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cb0_o_address = Signal(8)
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cb0_o_data = Signal(512)
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self.sync.rtio += [
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If(self.reset | cb0_ack,
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@ -89,7 +89,7 @@ class RTPacketRepeater(Module):
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cb_cmd = Signal(2)
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cb_timestamp = Signal(64)
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cb_chan_sel = Signal(24)
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cb_o_address = Signal(16)
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cb_o_address = Signal(8)
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cb_o_data = Signal(512)
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self.sync.rtio += [
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If(self.reset | cb_ack,
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@ -50,7 +50,7 @@ def get_m2s_layouts(alignment):
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plm.add_type("write", ("timestamp", 64),
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("chan_sel", 24),
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("address", 16),
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("address", 8),
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("extra_data_cnt", 8),
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("short_data", short_data_len))
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plm.add_type("buffer_space_request", ("destination", 8))
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