forked from M-Labs/artiq
kasli: don't pass rtio pll feedback through bufg
UG472: "The MMCM performance increases because the feedback clock is not subjected to noise on the core supply since it never passes through a block powered by this supply." Signed-off-by: Robert Jördens <rj@quartiq.de>
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@ -44,7 +44,7 @@ class _RTIOCRG(Module, AutoCSR):
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pll_locked = Signal()
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rtio_clk = Signal()
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rtiox4_clk = Signal()
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ext_clkout_clk = Signal()
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fb_clk = Signal()
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self.specials += [
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Instance("PLLE2_ADV",
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p_STARTUP_WAIT="FALSE", o_LOCKED=pll_locked,
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@ -57,13 +57,16 @@ class _RTIOCRG(Module, AutoCSR):
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# VCO @ 1.5GHz when using 125MHz input
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p_CLKFBOUT_MULT=12, p_DIVCLK_DIVIDE=1,
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i_CLKFBIN=self.cd_rtio.clk,
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i_CLKFBIN=fb_clk,
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i_RST=self._pll_reset.storage,
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o_CLKFBOUT=rtio_clk,
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o_CLKFBOUT=fb_clk,
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p_CLKOUT0_DIVIDE=3, p_CLKOUT0_PHASE=0.0,
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o_CLKOUT0=rtiox4_clk),
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o_CLKOUT0=rtiox4_clk,
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p_CLKOUT1_DIVIDE=12, p_CLKOUT1_PHASE=0.0,
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o_CLKOUT1=rtio_clk),
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Instance("BUFG", i_I=rtio_clk, o_O=self.cd_rtio.clk),
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Instance("BUFG", i_I=rtiox4_clk, o_O=self.cd_rtiox4.clk),
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