forked from M-Labs/artiq
kasli: only add moninj core if there are probes to monitor
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parent
5d31cf2268
commit
4499ef1748
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@ -133,8 +133,11 @@ class StandaloneBase(MiniSoC, AMPSoC):
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[self.rtio.cri, self.rtio_dma.cri],
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[self.rtio_core.cri])
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self.register_kernel_cpu_csrdevice("cri_con")
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self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)
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self.csr_devices.append("rtio_moninj")
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# Only add MonInj core if there is anything to monitor
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if any([len(c.probes) for c in rtio_channels]):
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self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)
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self.csr_devices.append("rtio_moninj")
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self.platform.add_false_path_constraints(
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self.crg.cd_sys.clk,
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@ -596,8 +599,10 @@ class MasterBase(MiniSoC, AMPSoC):
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fix_serdes_timing_path(platform)
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def add_rtio(self, rtio_channels):
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self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)
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self.csr_devices.append("rtio_moninj")
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# Only add MonInj core if there is anything to monitor
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if any([len(c.probes) for c in rtio_channels]):
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self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)
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self.csr_devices.append("rtio_moninj")
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self.submodules.rtio_core = rtio.Core(self.rtio_tsc, rtio_channels)
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self.csr_devices.append("rtio_core")
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@ -785,8 +790,10 @@ class SatelliteBase(BaseSoC):
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fix_serdes_timing_path(platform)
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def add_rtio(self, rtio_channels):
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self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)
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self.csr_devices.append("rtio_moninj")
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# Only add MonInj core if there is anything to monitor
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if any([len(c.probes) for c in rtio_channels]):
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self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)
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self.csr_devices.append("rtio_moninj")
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self.submodules.local_io = SyncRTIO(self.rtio_tsc, rtio_channels)
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self.comb += self.drtiosat.async_errors.eq(self.local_io.async_errors)
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