forked from M-Labs/artiq
firmware: Add Si5324 config for 125 MHz ext ref
PLL divider settings as suggested by DSPLLsim 5.1.
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dc7a642b26
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4d215cf541
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@ -137,8 +137,8 @@ fn startup() {
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#[cfg(si5324_as_synthesizer)]
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fn setup_si5324_as_synthesizer()
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{
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// 125MHz output, from 100MHz CLKIN2 reference, 586 Hz
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#[cfg(all(not(si5324_sayma_ref), rtio_frequency = "125.0", si5324_ext_ref))]
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// 125MHz output, from 100MHz CLKIN2 reference, 586 Hz loop bandwidth
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#[cfg(all(not(si5324_sayma_ref), rtio_frequency = "125.0", si5324_ext_ref, ext_ref_frequency = "100.0"))]
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const SI5324_SETTINGS: board_artiq::si5324::FrequencySettings
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= board_artiq::si5324::FrequencySettings {
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n1_hs : 10,
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@ -150,6 +150,19 @@ fn setup_si5324_as_synthesizer()
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bwsel : 4,
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crystal_ref: false
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};
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// 125MHz output, from 125MHz CLKIN2 reference, 606 Hz loop bandwidth
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#[cfg(all(not(si5324_sayma_ref), rtio_frequency = "125.0", si5324_ext_ref, ext_ref_frequency = "125.0"))]
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const SI5324_SETTINGS: board_artiq::si5324::FrequencySettings
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= board_artiq::si5324::FrequencySettings {
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n1_hs : 5,
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nc1_ls : 8,
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n2_hs : 7,
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n2_ls : 360,
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n31 : 63,
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n32 : 63,
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bwsel : 4,
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crystal_ref: false
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};
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// 125MHz output, from crystal, 7 Hz
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#[cfg(all(not(si5324_sayma_ref), rtio_frequency = "125.0", not(si5324_ext_ref)))]
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const SI5324_SETTINGS: board_artiq::si5324::FrequencySettings
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@ -159,6 +159,7 @@ class Opticlock(StandaloneBase):
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self.config["SI5324_AS_SYNTHESIZER"] = None
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self.config["SI5324_EXT_REF"] = None
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self.config["EXT_REF_FREQUENCY"] = "100.0"
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self.config["RTIO_FREQUENCY"] = "125.0"
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if hw_rev == "v1.0":
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# EEM clock fan-out from Si5324, not MMCX
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@ -291,6 +292,7 @@ class PTB2(StandaloneBase):
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self.config["SI5324_AS_SYNTHESIZER"] = None
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self.config["SI5324_EXT_REF"] = None
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self.config["EXT_REF_FREQUENCY"] = "100.0"
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self.config["RTIO_FREQUENCY"] = "125.0"
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if hw_rev == "v1.0":
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# EEM clock fan-out from Si5324, not MMCX
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