forked from M-Labs/artiq
wrpll: add simple thls compiler
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e4fff390a8
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267
artiq/gateware/wrpll/thls.py
Normal file
267
artiq/gateware/wrpll/thls.py
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import inspect
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import ast
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from copy import copy
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class Isn:
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def __init__(self, immediate=None, inputs=None, outputs=None):
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if inputs is None:
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inputs = []
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if outputs is None:
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outputs = []
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self.immediate = immediate
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self.inputs = inputs
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self.outputs = outputs
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def __repr__(self):
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r = "<"
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r += self.__class__.__name__
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if self.immediate is not None:
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r += " (" + str(self.immediate) + ")"
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for inp in self.inputs:
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r += " r" + str(inp)
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if self.outputs:
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r += " ->"
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for outp in self.outputs:
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r += " r" + str(outp)
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r += ">"
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return r
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class NopIsn(Isn):
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pass
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class AddIsn(Isn):
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pass
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class SubIsn(Isn):
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pass
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class MulIsn(Isn):
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pass
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class ShiftIsn(Isn):
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pass
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class CopyIsn(Isn):
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pass
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class InputIsn(Isn):
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pass
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class OutputIsn(Isn):
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pass
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class ASTCompiler:
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def __init__(self):
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self.program = []
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self.data = []
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self.next_ssa_reg = -1
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self.constants = dict()
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self.names = dict()
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self.globals = dict()
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def get_ssa_reg(self):
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r = self.next_ssa_reg
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self.next_ssa_reg -= 1
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return r
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def add_global(self, name):
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r = len(self.data)
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self.data.append(0)
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self.names[name] = r
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self.globals[name] = r
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return r
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def input(self, name):
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target = self.get_ssa_reg()
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self.program.append(InputIsn(outputs=[target]))
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self.names[name] = target
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def emit(self, node):
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if isinstance(node, ast.BinOp):
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left = self.emit(node.left)
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right = self.emit(node.right)
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if isinstance(node.op, ast.Add):
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cls = AddIsn
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elif isinstance(node.op, ast.Sub):
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cls = SubIsn
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elif isinstance(node.op, ast.Mult):
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cls = MulIsn
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else:
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raise NotImplementedError
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output = self.get_ssa_reg()
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self.program.append(cls(inputs=[left, right], outputs=[output]))
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return output
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elif isinstance(node, ast.Num):
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if node.n in self.constants:
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return self.constants[node.n]
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else:
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r = len(self.data)
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self.data.append(node.n)
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self.constants[node.n] = r
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return r
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elif isinstance(node, ast.Name):
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return self.names[node.id]
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elif isinstance(node, ast.Assign):
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output = self.emit(node.value)
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for target in node.targets:
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assert isinstance(target, ast.Name)
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self.names[target.id] = output
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elif isinstance(node, ast.Return):
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value = self.emit(node.value)
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self.program.append(OutputIsn(inputs=[value]))
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elif isinstance(node, ast.Global):
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pass
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else:
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raise NotImplementedError
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class Processor:
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def __init__(self, multiplier_stages=2):
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self.multiplier_stages = multiplier_stages
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def get_instruction_latency(self, isn):
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return {
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AddIsn: 2,
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SubIsn: 2,
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MulIsn: 1 + self.multiplier_stages,
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ShiftIsn: 2,
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CopyIsn: 1,
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InputIsn: 1
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}[isn.__class__]
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class Scheduler:
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def __init__(self, processor, reserved_data, program):
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self.processor = processor
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self.reserved_data = reserved_data
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self.used_registers = set(range(self.reserved_data))
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self.exits = dict()
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self.program = program
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self.remaining = copy(program)
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self.output = []
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def allocate_register(self):
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r = min(set(range(max(self.used_registers) + 2)) - self.used_registers)
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self.used_registers.add(r)
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return r
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def free_register(self, r):
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assert r >= self.reserved_data
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self.used_registers.discard(r)
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def find_inputs(self, cycle, isn):
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mapped_inputs = []
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for inp in isn.inputs:
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if inp >= 0:
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mapped_inputs.append(inp)
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else:
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found = False
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for i in range(cycle):
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if i in self.exits:
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r, rm = self.exits[i]
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if r == inp:
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mapped_inputs.append(rm)
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found = True
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break
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if not found:
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return None
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return mapped_inputs
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def schedule_one(self, isn):
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cycle = len(self.output)
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mapped_inputs = self.find_inputs(cycle, isn)
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if mapped_inputs is None:
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return False
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if isn.outputs:
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latency = self.processor.get_instruction_latency(isn)
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exit = cycle + latency
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if exit in self.exits:
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return False
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# Instruction can be scheduled
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self.remaining.remove(isn)
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for inp, minp in zip(isn.inputs, mapped_inputs):
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can_free = inp < 0 and all(inp != rinp for risn in self.remaining for rinp in risn.inputs)
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if can_free:
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self.free_register(minp)
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if isn.outputs:
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assert len(isn.outputs) == 1
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output = self.allocate_register()
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self.exits[exit] = (isn.outputs[0], output)
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self.output.append(isn.__class__(immediate=isn.immediate, inputs=mapped_inputs))
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return True
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def schedule(self):
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while self.remaining:
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success = False
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for isn in self.remaining:
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if self.schedule_one(isn):
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success = True
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break
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if not success:
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self.output.append(NopIsn())
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self.output += [NopIsn()]*(max(self.exits.keys()) - len(self.output) + 1)
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return self.output
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def pretty_print(self):
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for cycle, isn in enumerate(self.output):
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l = "{:4d} {:15}".format(cycle, str(isn))
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if cycle in self.exits:
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l += " -> r{}".format(self.exits[cycle][1])
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print(l)
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def compile(function):
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node = ast.parse(inspect.getsource(function))
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assert isinstance(node, ast.Module)
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assert len(node.body) == 1
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node = node.body[0]
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assert isinstance(node, ast.FunctionDef)
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assert len(node.args.args) == 1
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arg = node.args.args[0].arg
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body = node.body
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astcompiler = ASTCompiler()
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for node in body:
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if isinstance(node, ast.Global):
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for name in node.names:
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astcompiler.add_global(name)
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arg_r = astcompiler.input(arg)
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for node in body:
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astcompiler.emit(node)
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print(astcompiler.data)
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print(astcompiler.program)
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scheduler = Scheduler(Processor(), len(astcompiler.data), astcompiler.program)
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scheduler.schedule()
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scheduler.pretty_print()
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a = 0
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b = 0
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c = 0
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def foo(x):
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global a, b, c
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c = b
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b = a
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a = x
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return 4748*a + 259*b - 155*c
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compile(foo)
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