forked from M-Labs/artiq
sayma_rtm_drtio: add HMC clock chip and DAC control
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a8cf4c2b18
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@ -10,6 +10,7 @@ from migen.genlib.cdc import MultiReg
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from misoc.interconnect.csr import *
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from misoc.cores import gpio
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from misoc.cores import spi2
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from misoc.cores.a7_gtp import *
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from misoc.targets.sayma_rtm import BaseSoC, soc_sayma_rtm_args, soc_sayma_rtm_argdict
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from misoc.integration.builder import Builder, builder_args, builder_argdict
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@ -165,6 +166,31 @@ class _SatelliteBase(BaseSoC):
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self.csr_devices.append("rtio_crg")
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fix_serdes_timing_path(platform)
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# HMC clock chip and DAC control
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self.comb += platform.request("ad9154_rst_n", 0).eq(1)
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if self.hw_rev == "v2.0":
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self.comb += platform.request("ad9154_rst_n", 1).eq(1)
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self.submodules.converter_spi = spi2.SPIMaster(spi2.SPIInterface(
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platform.request("hmc_spi"),
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platform.request("ad9154_spi", 0),
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platform.request("ad9154_spi", 1)))
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self.csr_devices.append("converter_spi")
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self.submodules.hmc7043_reset = gpio.GPIOOut(
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platform.request("hmc7043_reset"), reset_out=1)
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self.csr_devices.append("hmc7043_reset")
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self.submodules.hmc7043_gpo = gpio.GPIOIn(
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platform.request("hmc7043_gpo"))
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self.csr_devices.append("hmc7043_gpo")
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if self.hw_rev == "v2.0":
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self.comb += platform.request("hmc830_pwr_en").eq(1)
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self.submodules.hmc7043_out_en = gpio.GPIOOut(
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platform.request("hmc7043_out_en"))
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self.csr_devices.append("hmc7043_out_en")
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self.config["HAS_HMC830_7043"] = None
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self.config["CONVERTER_SPI_HMC830_CS"] = 0
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self.config["CONVERTER_SPI_HMC7043_CS"] = 1
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self.config["HMC830_REF"] = "150"
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def add_rtio(self, rtio_channels):
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self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)
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self.csr_devices.append("rtio_moninj")
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