forked from M-Labs/artiq
wrpll: helper clock sanity check
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46a776d06e
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0499f83580
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@ -264,6 +264,14 @@ mod si549 {
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}
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}
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fn get_helper_frequency() -> u32 {
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unsafe { csr::wrpll::helper_frequency_start_write(1); }
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clock::spin_us(10_000);
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unsafe { csr::wrpll::helper_frequency_stop_write(1); }
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clock::spin_us(1);
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unsafe { csr::wrpll::helper_frequency_counter_read() }
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}
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pub fn init() {
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info!("initializing...");
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@ -281,6 +289,9 @@ pub fn init() {
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clock::spin_us(10_000); // Settling Time after FS Change
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unsafe { csr::wrpll::helper_reset_write(0); }
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clock::spin_us(1);
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info!("helper clock frequency: {}MHz", get_helper_frequency()/10000);
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info!("DDMTD test:");
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for _ in 0..20 {
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@ -1,11 +1,41 @@
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from migen import *
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from migen.genlib.resetsync import AsyncResetSynchronizer
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from migen.genlib.cdc import MultiReg, PulseSynchronizer
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from misoc.interconnect.csr import *
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from artiq.gateware.drtio.wrpll.si549 import Si549
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from artiq.gateware.drtio.wrpll.ddmtd import DDMTD
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class FrequencyCounter(Module, AutoCSR):
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def __init__(self):
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self.counter = CSRStatus(32)
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self.start = CSR()
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self.stop = CSR()
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ps_start = PulseSynchronizer("sys", "helper")
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ps_stop = PulseSynchronizer("sys", "helper")
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self.submodules += ps_start, ps_stop
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self.comb += [
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ps_start.i.eq(self.start.re & self.start.r),
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ps_stop.i.eq(self.stop.re & self.stop.r)
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]
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counter = Signal(32)
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self.specials += MultiReg(counter, self.counter.status)
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counting = Signal()
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self.sync.helper += [
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If(counting, counter.eq(counter + 1)),
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If(ps_start.o,
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counter.eq(0),
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counting.eq(1)
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),
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If(ps_stop.o, counting.eq(0))
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]
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class WRPLL(Module, AutoCSR):
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def __init__(self, helper_clk_pads, main_dcxo_i2c, helper_dxco_i2c, ddmtd_inputs, N=15):
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self.helper_reset = CSRStorage(reset=1)
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@ -21,6 +51,8 @@ class WRPLL(Module, AutoCSR):
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self.submodules.main_dcxo = Si549(main_dcxo_i2c)
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self.submodules.helper_dcxo = Si549(helper_dxco_i2c)
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self.submodules.helper_frequency = FrequencyCounter()
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ddmtd_counter = Signal(N)
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self.sync.helper += ddmtd_counter.eq(ddmtd_counter + 1)
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self.submodules.ddmtd_helper = DDMTD(ddmtd_counter, ddmtd_inputs.rec_clk)
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