forked from M-Labs/artiq
grabber: remove unused code
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4e77be0511
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@ -23,7 +23,6 @@ class Synchronizer(Module):
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for count in counts_in:
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count.attr.add("no_retiming")
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counts_rtio = [Signal.like(count) for count in counts_in]
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self.specials += [MultiReg(i, o, "rtio") for i, o in zip(counts_in, self.counts)]
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ps = PulseSynchronizer("cl", "rtio")
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