forked from M-Labs/artiq
gateware/eem: Force IOB=TRUE on Urukul SYNC output
Without this, the final register in the SYNC signal TTLClockGen isn't (always) placed in the I/O tile, leading to more jitter than necessary, and causing "double window" artefacts. See sinara-hw/Urukul#16 for more details. (Patch based on work by Weida Zhang, testing by various members of the community in Oxford and elsewhere.)
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@ -87,7 +87,7 @@ class Urukul(_EEM):
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),
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]
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ttls = [(6, eem, "io_update"),
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(7, eem, "dds_reset_sync_in")]
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(7, eem, "dds_reset_sync_in", Misc("IOB=TRUE"))]
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if eem_aux is not None:
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ttls += [(0, eem_aux, "sync_clk"),
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(1, eem_aux, "sync_in"),
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@ -97,12 +97,12 @@ class Urukul(_EEM):
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(5, eem_aux, "sw1"),
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(6, eem_aux, "sw2"),
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(7, eem_aux, "sw3")]
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for i, j, sig in ttls:
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for i, j, sig, *extra_args in ttls:
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ios.append(
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("urukul{}_{}".format(eem, sig), 0,
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Subsignal("p", Pins(_eem_pin(j, i, "p"))),
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Subsignal("n", Pins(_eem_pin(j, i, "n"))),
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IOStandard(iostandard)
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IOStandard(iostandard), *extra_args
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))
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return ios
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