forked from M-Labs/artiq
sayma_amc: cleanup (v2.0 only)
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e9b81f6e33
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@ -63,9 +63,10 @@ class SatelliteBase(BaseSoC):
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# Use SFP0 to connect to master (Kasli)
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self.comb += platform.request("sfp_tx_disable", 0).eq(0)
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drtio_data_pads = [platform.request("sfp", 0)]
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if self.hw_rev == "v2.0":
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drtio_data_pads.append(platform.request("rtm_amc_link"))
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drtio_data_pads = [
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platform.request("sfp", 0),
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platform.request("rtm_amc_link")
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]
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self.submodules.drtio_transceiver = gth_ultrascale.GTH(
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clock_pads=platform.request("cdr_clk_clean"),
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data_pads=drtio_data_pads,
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@ -119,8 +120,7 @@ class SatelliteBase(BaseSoC):
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self.add_csr_group("drtiorep", drtiorep_csr_group)
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self.config["RTIO_FREQUENCY"] = str(rtio_clk_freq/1e6)
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if self.hw_rev == "v2.0":
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self.comb += platform.request("filtered_clk_sel").eq(1)
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self.comb += platform.request("filtered_clk_sel").eq(1)
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self.submodules.siphaser = SiPhaser7Series(
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si5324_clkin=platform.request("si5324_clkin"),
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rx_synchronizer=self.rx_synchronizer,
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