forked from M-Labs/artiq
drtio: implement per-destination buffer space
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e95638e0a7
commit
1ef39a98a7
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@ -83,16 +83,6 @@ pub mod drtio {
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}
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}
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fn init_buffer_space(linkno: u8) {
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let linkidx = linkno as usize;
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unsafe {
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(csr::DRTIO[linkidx].o_get_buffer_space_write)(1);
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while (csr::DRTIO[linkidx].o_wait_read)() == 1 {}
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info!("[LINK#{}] buffer space is {}",
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linkno, (csr::DRTIO[linkidx].o_dbg_buffer_space_read)());
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}
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}
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fn ping_remote(linkno: u8, io: &Io) -> u32 {
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let mut count = 0;
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loop {
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@ -172,6 +162,19 @@ pub mod drtio {
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Ok(())
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}
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fn init_buffer_space(destination: u8, linkno: u8) {
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let linkno = linkno as usize;
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unsafe {
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(csr::DRTIO[linkno].destination_write)(destination);
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(csr::DRTIO[linkno].force_destination_write)(1);
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(csr::DRTIO[linkno].o_get_buffer_space_write)(1);
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while (csr::DRTIO[linkno].o_wait_read)() == 1 {}
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info!("[DEST#{}] buffer space is {}",
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destination, (csr::DRTIO[linkno].o_dbg_buffer_space_read)());
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(csr::DRTIO[linkno].force_destination_write)(0);
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}
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}
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fn process_unsolicited_aux(linkno: u8) {
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match drtioaux::recv_link(linkno) {
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Ok(Some(packet)) => warn!("[LINK#{}] unsolicited aux packet: {:?}", linkno, packet),
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@ -248,7 +251,7 @@ pub mod drtio {
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Ok(drtioaux::Packet::DestinationOkReply) => {
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info!("[DEST#{}] destination is up", destination);
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up_destinations[destination] = true;
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/* TODO: get buffer space */
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init_buffer_space(destination as u8, linkno);
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},
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Ok(packet) => error!("[DEST#{}] received unexpected aux packet: {:?}", destination, packet),
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Err(e) => error!("[DEST#{}] communication failed ({})", destination, e)
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@ -281,7 +284,6 @@ pub mod drtio {
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if ping_count > 0 {
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info!("[LINK#{}] remote replied after {} packets", linkno, ping_count);
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set_link_up(linkno, true);
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init_buffer_space(linkno);
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if let Err(e) = sync_tsc(&io, linkno) {
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error!("[LINK#{}] failed to sync TSC ({})", linkno, e);
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}
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@ -19,6 +19,9 @@ class _CSRs(AutoCSR):
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self.set_time = CSR()
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self.underflow_margin = CSRStorage(16, reset=300)
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self.force_destination = CSRStorage()
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self.destination = CSRStorage(8)
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self.o_get_buffer_space = CSR()
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self.o_dbg_buffer_space = CSRStatus(16)
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self.o_dbg_buffer_space_req_cnt = CSRStatus(32)
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@ -71,11 +74,17 @@ class RTController(Module):
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If(self.csrs.set_time.re, rt_packet.set_time_stb.eq(1))
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]
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# chan_sel forcing
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chan_sel = Signal(24)
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self.comb += chan_sel.eq(Mux(self.csrs.force_destination.storage,
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self.csrs.destination.storage << 16,
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self.cri.chan_sel))
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# common packet fields
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rt_packet_buffer_request = Signal()
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rt_packet_read_request = Signal()
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self.comb += [
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rt_packet.sr_chan_sel.eq(self.cri.chan_sel),
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rt_packet.sr_chan_sel.eq(chan_sel),
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rt_packet.sr_address.eq(self.cri.o_address),
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rt_packet.sr_data.eq(self.cri.o_data),
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rt_packet.sr_timestamp.eq(self.cri.timestamp),
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@ -112,7 +121,22 @@ class RTController(Module):
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self.comb += cond_underflow.eq((self.cri.timestamp[tsc.glbl_fine_ts_width:]
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- self.csrs.underflow_margin.storage[tsc.glbl_fine_ts_width:]) < tsc.coarse_ts_sys)
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buffer_space = Signal(16)
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# buffer space
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buffer_space = Memory(16, 256)
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buffer_space_port = buffer_space.get_port(write_capable=True)
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self.specials += buffer_space, buffer_space_port
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buffer_space_load = Signal()
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buffer_space_dec = Signal()
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self.comb += [
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buffer_space_port.adr.eq(chan_sel[16:]),
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buffer_space_port.we.eq(buffer_space_load | buffer_space_dec),
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If(buffer_space_load,
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buffer_space_port.dat_w.eq(rt_packet.buffer_space)
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).Else(
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buffer_space_port.dat_w.eq(buffer_space_port.dat_r - 1)
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)
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]
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# input status
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i_status_wait_event = Signal()
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@ -158,8 +182,8 @@ class RTController(Module):
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o_status_wait.eq(1),
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rt_packet.sr_stb.eq(1),
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If(rt_packet.sr_ack,
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NextValue(buffer_space, buffer_space - 1),
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If(buffer_space <= 1,
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buffer_space_dec.eq(1),
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If(buffer_space_port.dat_r <= 1,
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NextState("GET_BUFFER_SPACE")
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).Else(
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NextState("IDLE")
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@ -177,7 +201,7 @@ class RTController(Module):
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)
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fsm.act("GET_BUFFER_SPACE_REPLY",
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o_status_wait.eq(1),
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NextValue(buffer_space, rt_packet.buffer_space),
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buffer_space_load.eq(1),
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rt_packet.buffer_space_not_ack.eq(1),
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If(rt_packet.buffer_space_not,
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If(rt_packet.buffer_space != 0,
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@ -211,7 +235,7 @@ class RTController(Module):
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)
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# debug CSRs
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self.comb += self.csrs.o_dbg_buffer_space.status.eq(buffer_space),
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self.comb += self.csrs.o_dbg_buffer_space.status.eq(buffer_space_port.dat_r),
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self.sync += \
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If((rt_packet.sr_stb & rt_packet.sr_ack & rt_packet_buffer_request),
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self.csrs.o_dbg_buffer_space_req_cnt.status.eq(
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