forked from M-Labs/artiq
rtio: remove incorrect comment
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@ -61,8 +61,6 @@ class Interface(Record):
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class KernelInitiator(Module, AutoCSR):
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def __init__(self, tsc, cri=None):
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self.target = CSRStorage(32)
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# monotonic, may lag behind the counter in the IO clock domain, but
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# not be ahead of it.
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self.timestamp = CSRStorage(64)
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# Writing timestamp clears o_data. This implements automatic
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