forked from M-Labs/artiq
ttl_serdes_ultrascale: use GTH clock domains
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@ -3,9 +3,6 @@ from migen import *
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from artiq.gateware.rtio.phy import ttl_serdes_generic
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# SERDES clocks are in dedicated domains to make the implementation
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# of the convoluted clocking schemes from AR#67885 less tedious.
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class _OSERDESE3(Module):
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def __init__(self, dw, pad, pad_n=None):
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self.o = Signal(dw)
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@ -20,8 +17,8 @@ class _OSERDESE3(Module):
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p_IS_CLK_INVERTED=0, p_IS_CLKDIV_INVERTED=0, p_IS_RST_INVERTED=0,
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o_OQ=pad_o, o_T_OUT=self.t_out,
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i_RST=ResetSignal("rtio_serdes"),
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i_CLK=ClockSignal("rtiox_serdes"), i_CLKDIV=ClockSignal("rtio_serdes"),
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i_RST=ResetSignal("rtio"),
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i_CLK=ClockSignal("rtiox"), i_CLKDIV=ClockSignal("rtio"),
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i_D=self.o, i_T=self.t_in)
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if pad_n is None:
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self.comb += pad.eq(pad_o)
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@ -49,11 +46,11 @@ class _ISERDESE3(Module):
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p_DATA_WIDTH=dw,
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i_D=pad_i,
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i_RST=ResetSignal("rtio_serdes"),
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i_RST=ResetSignal("rtio"),
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i_FIFO_RD_EN=0,
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i_CLK=ClockSignal("rtiox_serdes"),
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i_CLK_B=ClockSignal("rtiox_serdes"), # locally inverted
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i_CLKDIV=ClockSignal("rtio_serdes"),
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i_CLK=ClockSignal("rtiox"),
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i_CLK_B=ClockSignal("rtiox"), # locally inverted
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i_CLKDIV=ClockSignal("rtio"),
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o_Q=Cat(*[self.i[i] for i in reversed(range(dw))]))
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if pad_n is None:
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self.comb += pad_i.eq(pad)
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