forked from M-Labs/artiq
gateware/suservo: Sign-extend data on RTIO read-back
See GitHub #1327 for original patch by Brad Bondurant.
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@ -23,6 +23,13 @@ class RTServoCtrl(Module):
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]
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def _eq_sign_extend(t, s):
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"""Assign target signal `t` from source `s`, sign-extending `s` to the
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full width.
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"""
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return t.eq(Cat(s, Replicate(s[-1], len(t) - len(s))))
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class RTServoMem(Module):
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"""All-channel all-profile coefficient and state RTIO control
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interface.
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@ -49,6 +56,11 @@ class RTServoMem(Module):
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IIR state mem | 0 | 1
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config (write) | 1 | 1
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status (read) | 1 | 1
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Values returned to the user on the Python side of the RTIO interface are
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32 bit, so we sign-extend all values from w.coeff to that width. This works
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(instead of having to decide whether to sign- or zero-extend per address), as
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all unsigned values are less wide than w.coeff.
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"""
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def __init__(self, w, servo):
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m_coeff = servo.iir.m_coeff.get_port(write_capable=True,
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@ -66,6 +78,9 @@ class RTServoMem(Module):
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assert len(m_coeff.dat_w) == 2*w.coeff
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# ensure that the DDS word data fits into the coefficient mem
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assert w.coeff >= w.word
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# ensure all unsigned values will be zero-extended on sign extension
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assert w.word < w.coeff
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assert 8 + w.dly < w.coeff
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# coeff, profile, channel, 2 mems, rw
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internal_address_width = 3 + w.profile + w.channel + 1 + 1
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@ -77,7 +92,7 @@ class RTServoMem(Module):
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address_width=rtlink_address_width,
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enable_replace=False),
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rtlink.IInterface(
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data_width=w.coeff,
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data_width=32,
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timestamped=False)
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)
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@ -152,7 +167,7 @@ class RTServoMem(Module):
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]
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self.comb += [
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self.rtlink.i.stb.eq(read),
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self.rtlink.i.data.eq(
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_eq_sign_extend(self.rtlink.i.data,
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Mux(read_state,
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Mux(read_config,
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status,
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