forked from M-Labs/artiq
sayma_amc: fix Master timing constraints
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parent
6c52359e59
commit
4cb9f77fd8
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@ -507,16 +507,16 @@ class Master(MiniSoC, AMPSoC):
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self.add_memory_group("drtioaux_mem", drtioaux_memory_group)
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rtio_clk_period = 1e9/rtio_clk_freq
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gth = self.drtio_transceiver.gths[0]
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platform.add_period_constraint(gth.txoutclk, rtio_clk_period/2)
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platform.add_period_constraint(gth.rxoutclk, rtio_clk_period)
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gth0 = self.drtio_transceiver.gths[0]
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platform.add_period_constraint(gth0.txoutclk, rtio_clk_period/2)
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platform.add_period_constraint(gth0.rxoutclk, rtio_clk_period)
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platform.add_false_path_constraints(
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self.crg.cd_sys.clk,
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gth.txoutclk, gth.rxoutclk)
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gth0.txoutclk, gth0.rxoutclk)
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for gth in self.drtio_transceiver.gths[1:]:
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platform.add_period_constraint(gth.rxoutclk, rtio_clk_period)
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platform.add_false_path_constraints(
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self.crg.cd_sys.clk, gth.rxoutclk)
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self.crg.cd_sys.clk, gth0.txoutclk, gth.rxoutclk)
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self.rtio_channels = rtio_channels = []
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for i in range(4):
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