rtio: use BlindTransfer from Migen

artiq/gateware/drtio/rt_controller_repeater.py

@@ -1,9 +1,8 @@
 from migen import *
-from migen.genlib.cdc import MultiReg
+from migen.genlib.cdc import MultiReg, BlindTransfer
 
 from misoc.interconnect.csr import *
 
-from artiq.gateware.rtio.cdc import BlindTransfer
 from artiq.gateware.drtio.cdc import CrossDomainRequest
 
 

artiq/gateware/drtio/rt_errors_satellite.py

@@ -1,9 +1,9 @@
 """Protocol error reporting for satellites."""
 
 from migen import *
-from misoc.interconnect.csr import *
+from migen.genlib.cdc import BlindTransfer
 
-from artiq.gateware.rtio.cdc import BlindTransfer
+from misoc.interconnect.csr import *
 
 
 class RTErrorsSatellite(Module, AutoCSR):
@@ -27,7 +27,7 @@ class RTErrorsSatellite(Module, AutoCSR):
                     data_width = len(din)
                 else:
                     data_width = 0
-                xfer = BlindTransfer(odomain="sys", data_width=data_width)
+                xfer = BlindTransfer("rio", "sys", data_width=data_width)
                 self.submodules += xfer
 
                 if detect_edges:

artiq/gateware/drtio/rt_packet_master.py

@@ -3,8 +3,9 @@
 from migen import *
 from migen.genlib.fsm import *
 from migen.genlib.fifo import AsyncFIFO
+from migen.genlib.cdc import BlindTransfer
 
-from artiq.gateware.rtio.cdc import GrayCodeTransfer, BlindTransfer
+from artiq.gateware.rtio.cdc import GrayCodeTransfer
 from artiq.gateware.drtio.cdc import CrossDomainRequest, CrossDomainNotification
 from artiq.gateware.drtio.rt_serializer import *
 

artiq/gateware/rtio/cdc.py

@@ -2,7 +2,7 @@ from migen import *
 from migen.genlib.cdc import *
 
 
-__all__ = ["GrayCodeTransfer", "BlindTransfer"]
+__all__ = ["GrayCodeTransfer"]
 
 
 # note: transfer is in rtio/sys domains and not affected by the reset CSRs
@@ -26,36 +26,3 @@ class GrayCodeTransfer(Module):
         for i in reversed(range(width-1)):
             self.comb += value_sys[i].eq(value_sys[i+1] ^ value_gray_sys[i])
         self.sync += self.o.eq(value_sys)
-
-
-class BlindTransfer(Module):
-    def __init__(self, idomain="rio", odomain="rsys", data_width=0):
-        self.i = Signal()
-        self.o = Signal()
-        if data_width:
-            self.data_i = Signal(data_width)
-            self.data_o = Signal(data_width, reset_less=True)
-
-        # # #
-
-        ps = PulseSynchronizer(idomain, odomain)
-        ps_ack = PulseSynchronizer(odomain, idomain)
-        self.submodules += ps, ps_ack
-        blind = Signal()
-        isync = getattr(self.sync, idomain)
-        isync += [
-            If(self.i, blind.eq(1)),
-            If(ps_ack.o, blind.eq(0))
-        ]
-        self.comb += [
-            ps.i.eq(self.i & ~blind),
-            ps_ack.i.eq(ps.o),
-            self.o.eq(ps.o)
-        ]
-
-        if data_width:
-            bxfer_data = Signal(data_width, reset_less=True)
-            isync += If(ps.i, bxfer_data.eq(self.data_i))
-            bxfer_data.attr.add("no_retiming")
-            self.specials += MultiReg(bxfer_data, self.data_o,
-                                      odomain=odomain)

artiq/gateware/rtio/core.py

@@ -3,12 +3,12 @@ from operator import and_
 
 from migen import *
 from migen.genlib.resetsync import AsyncResetSynchronizer
+from migen.genlib.cdc import BlindTransfer
 from misoc.interconnect.csr import *
 
 from artiq.gateware.rtio import cri
 from artiq.gateware.rtio import rtlink
 from artiq.gateware.rtio.channel import *
-from artiq.gateware.rtio.cdc import *
 from artiq.gateware.rtio.sed.core import *
 from artiq.gateware.rtio.input_collector import *
 
@@ -79,8 +79,8 @@ class Core(Module, AutoCSR):
         self.submodules += inputs
 
         # Asychronous output errors
-        o_collision_sync = BlindTransfer(data_width=16)
-        o_busy_sync = BlindTransfer(data_width=16)
+        o_collision_sync = BlindTransfer("rio", "rsys", data_width=16)
+        o_busy_sync = BlindTransfer("rio", "rsys", data_width=16)
         self.submodules += o_collision_sync, o_busy_sync
         o_collision = Signal()
         o_busy = Signal()

artiq/gateware/rtio/input_collector.py

@@ -1,10 +1,10 @@
 from migen import *
 from migen.genlib.record import Record
 from migen.genlib.fifo import *
+from migen.genlib.cdc import BlindTransfer
 
 from artiq.gateware.rtio import cri
 from artiq.gateware.rtio import rtlink
-from artiq.gateware.rtio.cdc import *
 
 
 __all__ = ["InputCollector"]
@@ -85,7 +85,7 @@ class InputCollector(Module):
             if mode == "sync":
                 overflow_trigger = overflow_io
             elif mode == "async":
-                overflow_transfer = BlindTransfer()
+                overflow_transfer = BlindTransfer("rio", "rsys")
                 self.submodules += overflow_transfer
                 self.comb += overflow_transfer.i.eq(overflow_io)
                 overflow_trigger = overflow_transfer.o