forked from M-Labs/artiq
wrpll: drive helper clock domain
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4a03ca928d
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354d82cfe3
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@ -1,3 +1,5 @@
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use board_misoc::{csr, clock};
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mod i2c {
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use board_misoc::{csr, clock};
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@ -272,6 +274,8 @@ mod si549 {
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pub fn init() {
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info!("initializing...");
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unsafe { csr::wrpll::helper_reset_write(1); }
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#[cfg(rtio_frequency = "125.0")]
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let (m_hsdiv, m_lsdiv, m_fbdiv) = (0x017, 2, 0x04b5badb98a);
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#[cfg(rtio_frequency = "125.0")]
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@ -281,6 +285,9 @@ pub fn init() {
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.expect("cannot initialize main Si549");
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si549::program(i2c::Dcxo::Helper, h_hsdiv, h_lsdiv, h_fbdiv)
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.expect("cannot initialize helper Si549");
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clock::spin_us(10_000); // Settling Time after FS Change
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unsafe { csr::wrpll::helper_reset_write(0); }
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}
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pub fn select_recovered_clock(rc: bool) {
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@ -1,10 +1,21 @@
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from migen import *
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from migen.genlib.resetsync import AsyncResetSynchronizer
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from misoc.interconnect.csr import *
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from artiq.gateware.drtio.wrpll.si549 import Si549
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class WRPLL(Module, AutoCSR):
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def __init__(self, main_dcxo_i2c, helper_dxco_i2c):
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def __init__(self, helper_clk_pads, main_dcxo_i2c, helper_dxco_i2c):
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self.helper_reset = CSRStorage(reset=1)
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self.clock_domains.cd_helper = ClockDomain()
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self.helper_reset.storage.attr.add("no_retiming")
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self.specials += [
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Instance("IBUFGDS", i_I=helper_clk_pads.p, i_IB=helper_clk_pads.n,
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o_O=self.cd_helper.clk),
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AsyncResetSynchronizer(self.cd_helper, self.helper_reset.storage)
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]
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self.submodules.main_dcxo = Si549(main_dcxo_i2c)
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self.submodules.helper_dcxo = Si549(helper_dxco_i2c)
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@ -137,6 +137,7 @@ class SatelliteBase(MiniSoC):
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platform.request("ddmtd_helper_dcxo_oe").eq(1)
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]
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self.submodules.wrpll = WRPLL(
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helper_clk_pads=platform.request("ddmtd_helper_clk"),
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main_dcxo_i2c=platform.request("ddmtd_main_dcxo_i2c"),
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helper_dxco_i2c=platform.request("ddmtd_helper_dcxo_i2c"))
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self.csr_devices.append("wrpll")
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