forked from M-Labs/artiq
wrpll: i2c functions, select_recovered_clock placeholder
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449d2c4f08
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4832bfb08c
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@ -26,6 +26,8 @@ pub mod rpc_queue;
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#[cfg(has_si5324)]
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pub mod si5324;
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#[cfg(has_wrpll)]
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pub mod wrpll;
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#[cfg(has_hmc830_7043)]
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pub mod hmc830_7043;
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@ -0,0 +1,190 @@
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mod i2c {
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use board_misoc::{csr, clock};
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#[derive(Debug, Clone, Copy)]
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pub enum Dcxo {
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Main,
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Helper
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}
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fn half_period() { clock::spin_us(100) }
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const SDA_MASK: u8 = 2;
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const SCL_MASK: u8 = 1;
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fn sda_i(dcxo: Dcxo) -> bool {
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let reg = match dcxo {
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Dcxo::Main => unsafe { csr::wrpll::main_dcxo_gpio_in_read() },
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Dcxo::Helper => unsafe { csr::wrpll::helper_dcxo_gpio_in_read() },
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};
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reg & SDA_MASK != 0
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}
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fn sda_oe(dcxo: Dcxo, oe: bool) {
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let reg = match dcxo {
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Dcxo::Main => unsafe { csr::wrpll::main_dcxo_gpio_oe_read() },
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Dcxo::Helper => unsafe { csr::wrpll::helper_dcxo_gpio_oe_read() },
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};
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let reg = if oe { reg | SDA_MASK } else { reg & !SDA_MASK };
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match dcxo {
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Dcxo::Main => unsafe { csr::wrpll::main_dcxo_gpio_oe_write(reg) },
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Dcxo::Helper => unsafe { csr::wrpll::helper_dcxo_gpio_oe_write(reg) }
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}
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}
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fn sda_o(dcxo: Dcxo, o: bool) {
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let reg = match dcxo {
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Dcxo::Main => unsafe { csr::wrpll::main_dcxo_gpio_out_read() },
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Dcxo::Helper => unsafe { csr::wrpll::helper_dcxo_gpio_out_read() },
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};
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let reg = if o { reg | SDA_MASK } else { reg & !SDA_MASK };
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match dcxo {
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Dcxo::Main => unsafe { csr::wrpll::main_dcxo_gpio_out_write(reg) },
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Dcxo::Helper => unsafe { csr::wrpll::helper_dcxo_gpio_out_write(reg) }
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}
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}
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fn scl_oe(dcxo: Dcxo, oe: bool) {
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let reg = match dcxo {
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Dcxo::Main => unsafe { csr::wrpll::main_dcxo_gpio_oe_read() },
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Dcxo::Helper => unsafe { csr::wrpll::helper_dcxo_gpio_oe_read() },
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};
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let reg = if oe { reg | SCL_MASK } else { reg & !SCL_MASK };
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match dcxo {
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Dcxo::Main => unsafe { csr::wrpll::main_dcxo_gpio_oe_write(reg) },
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Dcxo::Helper => unsafe { csr::wrpll::helper_dcxo_gpio_oe_write(reg) }
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}
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}
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fn scl_o(dcxo: Dcxo, o: bool) {
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let reg = match dcxo {
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Dcxo::Main => unsafe { csr::wrpll::main_dcxo_gpio_out_read() },
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Dcxo::Helper => unsafe { csr::wrpll::helper_dcxo_gpio_out_read() },
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};
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let reg = if o { reg | SCL_MASK } else { reg & !SCL_MASK };
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match dcxo {
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Dcxo::Main => unsafe { csr::wrpll::main_dcxo_gpio_out_write(reg) },
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Dcxo::Helper => unsafe { csr::wrpll::helper_dcxo_gpio_out_write(reg) }
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}
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}
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pub fn init(dcxo: Dcxo) -> Result<(), &'static str> {
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// Set SCL as output, and high level
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scl_o(dcxo, true);
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scl_oe(dcxo, true);
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// Prepare a zero level on SDA so that sda_oe pulls it down
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sda_o(dcxo, false);
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// Release SDA
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sda_oe(dcxo, false);
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// Check the I2C bus is ready
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half_period();
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half_period();
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if !sda_i(dcxo) {
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// Try toggling SCL a few times
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for _bit in 0..8 {
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scl_o(dcxo, false);
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half_period();
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scl_o(dcxo, true);
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half_period();
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}
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}
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if !sda_i(dcxo) {
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return Err("SDA is stuck low and doesn't get unstuck");
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}
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Ok(())
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}
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pub fn start(dcxo: Dcxo) {
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// Set SCL high then SDA low
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scl_o(dcxo, true);
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half_period();
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sda_oe(dcxo, true);
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half_period();
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}
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pub fn restart(dcxo: Dcxo) {
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// Set SCL low then SDA high */
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scl_o(dcxo, false);
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half_period();
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sda_oe(dcxo, false);
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half_period();
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// Do a regular start
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start(dcxo);
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}
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pub fn stop(dcxo: Dcxo) {
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// First, make sure SCL is low, so that the target releases the SDA line
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scl_o(dcxo, false);
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half_period();
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// Set SCL high then SDA high
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sda_oe(dcxo, true);
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scl_o(dcxo, true);
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half_period();
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sda_oe(dcxo, false);
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half_period();
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}
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pub fn write(dcxo: Dcxo, data: u8) -> bool {
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// MSB first
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for bit in (0..8).rev() {
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// Set SCL low and set our bit on SDA
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scl_o(dcxo, false);
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sda_oe(dcxo, data & (1 << bit) == 0);
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half_period();
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// Set SCL high ; data is shifted on the rising edge of SCL
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scl_o(dcxo, true);
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half_period();
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}
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// Check ack
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// Set SCL low, then release SDA so that the I2C target can respond
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scl_o(dcxo, false);
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half_period();
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sda_oe(dcxo, false);
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// Set SCL high and check for ack
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scl_o(dcxo, true);
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half_period();
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// returns true if acked (I2C target pulled SDA low)
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!sda_i(dcxo)
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}
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pub fn read(dcxo: Dcxo, ack: bool) -> u8 {
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// Set SCL low first, otherwise setting SDA as input may cause a transition
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// on SDA with SCL high which will be interpreted as START/STOP condition.
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scl_o(dcxo, false);
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half_period(); // make sure SCL has settled low
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sda_oe(dcxo, false);
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let mut data: u8 = 0;
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// MSB first
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for bit in (0..8).rev() {
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scl_o(dcxo, false);
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half_period();
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// Set SCL high and shift data
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scl_o(dcxo, true);
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half_period();
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if sda_i(dcxo) { data |= 1 << bit }
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}
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// Send ack
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// Set SCL low and pull SDA low when acking
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scl_o(dcxo, false);
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if ack { sda_oe(dcxo, true) }
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half_period();
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// then set SCL high
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scl_o(dcxo, true);
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half_period();
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data
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}
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}
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pub fn init() {
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info!("initializing...");
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i2c::init(i2c::Dcxo::Main);
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i2c::init(i2c::Dcxo::Helper);
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}
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pub fn select_recovered_clock(rc: bool) {
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info!("select_recovered_clock: {}", rc);
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}
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@ -9,7 +9,11 @@ extern crate board_artiq;
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use core::convert::TryFrom;
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use board_misoc::{csr, irq, ident, clock, uart_logger, i2c};
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use board_artiq::{spi, si5324, drtioaux};
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#[cfg(has_si5324)]
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use board_artiq::si5324;
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#[cfg(has_wrpll)]
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use board_artiq::wrpll;
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use board_artiq::{spi, drtioaux};
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use board_artiq::drtio_routing;
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#[cfg(has_hmc830_7043)]
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use board_artiq::hmc830_7043;
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@ -413,7 +417,7 @@ fn hardware_tick(ts: &mut u64) {
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}
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}
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#[cfg(rtio_frequency = "150.0")]
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#[cfg(all(has_si5324, rtio_frequency = "150.0"))]
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const SI5324_SETTINGS: si5324::FrequencySettings
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= si5324::FrequencySettings {
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n1_hs : 6,
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@ -426,7 +430,7 @@ const SI5324_SETTINGS: si5324::FrequencySettings
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crystal_ref: true
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};
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#[cfg(rtio_frequency = "125.0")]
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#[cfg(all(has_si5324, rtio_frequency = "125.0"))]
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const SI5324_SETTINGS: si5324::FrequencySettings
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= si5324::FrequencySettings {
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n1_hs : 5,
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@ -448,8 +452,13 @@ pub extern fn main() -> i32 {
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info!("software ident {}", csr::CONFIG_IDENTIFIER_STR);
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info!("gateware ident {}", ident::read(&mut [0; 64]));
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i2c::init().expect("I2C initialization failed");
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si5324::setup(&SI5324_SETTINGS, si5324::Input::Ckin1).expect("cannot initialize Si5324");
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#[cfg(has_si5324)]
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{
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i2c::init().expect("I2C initialization failed");
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si5324::setup(&SI5324_SETTINGS, si5324::Input::Ckin1).expect("cannot initialize Si5324");
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}
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#[cfg(has_wrpll)]
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wrpll::init();
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unsafe {
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csr::drtio_transceiver::stable_clkin_write(1);
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}
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@ -490,8 +499,13 @@ pub extern fn main() -> i32 {
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}
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info!("uplink is up, switching to recovered clock");
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si5324::siphaser::select_recovered_clock(true).expect("failed to switch clocks");
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si5324::siphaser::calibrate_skew().expect("failed to calibrate skew");
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#[cfg(has_si5324)]
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{
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si5324::siphaser::select_recovered_clock(true).expect("failed to switch clocks");
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si5324::siphaser::calibrate_skew().expect("failed to calibrate skew");
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}
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#[cfg(has_wrpll)]
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wrpll::select_recovered_clock(true);
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#[cfg(has_jdcg)]
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{
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@ -561,8 +575,11 @@ pub extern fn main() -> i32 {
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drtiosat_reset_phy(true);
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drtiosat_reset(true);
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drtiosat_tsc_loaded();
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info!("uplink is down, switching to local crystal clock");
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info!("uplink is down, switching to local oscillator clock");
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#[cfg(has_si5324)]
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si5324::siphaser::select_recovered_clock(false).expect("failed to switch clocks");
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#[cfg(has_wrpll)]
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wrpll::select_recovered_clock(false);
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}
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}
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@ -130,26 +130,10 @@ class SatelliteBase(MiniSoC):
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self.add_csr_group("drtiorep", drtiorep_csr_group)
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self.config["RTIO_FREQUENCY"] = str(rtio_clk_freq/1e6)
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self.comb += platform.request("filtered_clk_sel").eq(1)
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self.submodules.siphaser = SiPhaser7Series(
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si5324_clkin=platform.request("si5324_clkin"),
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rx_synchronizer=self.rx_synchronizer,
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ultrascale=True,
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rtio_clk_freq=rtio_clk_freq)
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platform.add_false_path_constraints(
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self.crg.cd_sys.clk, self.siphaser.mmcm_freerun_output)
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self.csr_devices.append("siphaser")
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self.submodules.si5324_rst_n = gpio.GPIOOut(platform.request("si5324").rst_n)
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self.csr_devices.append("si5324_rst_n")
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i2c = self.platform.request("i2c")
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self.submodules.i2c = gpio.GPIOTristate([i2c.scl, i2c.sda])
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self.csr_devices.append("i2c")
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self.config["I2C_BUS_COUNT"] = 1
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self.config["HAS_SI5324"] = None
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if with_wrpll:
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# TODO: check OE polarity (depends on what was installed on the boards)
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self.comb += [
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platform.request("filtered_clk_sel").eq(0),
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platform.request("ddmtd_main_dcxo_oe").eq(1),
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platform.request("ddmtd_helper_dcxo_oe").eq(1)
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]
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@ -157,6 +141,23 @@ class SatelliteBase(MiniSoC):
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main_dcxo_i2c=platform.request("ddmtd_main_dcxo_i2c"),
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helper_dxco_i2c=platform.request("ddmtd_helper_dcxo_i2c"))
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self.csr_devices.append("wrpll")
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else:
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self.comb += platform.request("filtered_clk_sel").eq(1)
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self.submodules.siphaser = SiPhaser7Series(
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si5324_clkin=platform.request("si5324_clkin"),
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rx_synchronizer=self.rx_synchronizer,
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ultrascale=True,
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rtio_clk_freq=rtio_clk_freq)
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platform.add_false_path_constraints(
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self.crg.cd_sys.clk, self.siphaser.mmcm_freerun_output)
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self.csr_devices.append("siphaser")
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self.submodules.si5324_rst_n = gpio.GPIOOut(platform.request("si5324").rst_n)
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self.csr_devices.append("si5324_rst_n")
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i2c = self.platform.request("i2c")
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self.submodules.i2c = gpio.GPIOTristate([i2c.scl, i2c.sda])
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self.csr_devices.append("i2c")
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self.config["I2C_BUS_COUNT"] = 1
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self.config["HAS_SI5324"] = None
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rtio_clk_period = 1e9/rtio_clk_freq
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gth = self.drtio_transceiver.gths[0]
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