forked from M-Labs/artiq
sayma_amc: use more selective IOBUFDS false path
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@ -406,9 +406,9 @@ def workaround_us_lvds_tristate(platform):
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# timing analysis. Disable the latter for IOBUFDS.
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# See:
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# https://forums.xilinx.com/t5/Timing-Analysis/Delay-890-ns-in-OBUFTDS-in-Kintex-UltraScale/td-p/868364
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# FIXME: this is a bit zealous. Xilinx SR in progress to find a more selective command.
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platform.add_platform_command(
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"set_false_path -through [get_pins -filter {{REF_PIN_NAME == O}} -of [get_cells -filter {{REF_NAME == IOBUFDS}}]]")
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"set_false_path -through [get_pins -filter {{REF_PIN_NAME == T}} -of [get_cells -filter {{REF_NAME == IOBUFDS}}]]"
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" -through [get_pins -filter {{REF_PIN_NAME == O}} -of [get_cells -filter {{REF_NAME == IOBUFDS}}]]")
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class Master(MiniSoC, AMPSoC):
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