Sebastien Bourdeauducq
ccdc741e73
sayma_amc: fix --sfp argument
2020-12-07 18:02:36 +08:00
Sebastien Bourdeauducq
ea95d91428
wrpll: separate collector reset
2020-11-09 17:57:13 +08:00
Robert Jördens
a9dd0a268c
Merge pull request #1533 from m-labs/phaser
...
Phaser
2020-10-19 09:30:12 +02:00
Robert Jördens
30d1acee9f
fastlink: fix fastino style link
2020-10-18 20:43:21 +00:00
Robert Jördens
d98357051c
add ref data
2020-10-18 20:43:21 +00:00
Robert Jördens
139385a571
fastlink: add fastino test
2020-10-18 17:11:09 +00:00
Sebastien Bourdeauducq
d185f1ac67
wrpll: fix mulshift (2)
2020-10-17 00:32:02 +08:00
Sebastien Bourdeauducq
3f076bf79b
wrpll: fix mulshift
2020-10-16 22:05:37 +08:00
hartytp
a058be2ede
wrpll: fix test_helper_collector
2020-10-08 19:43:12 +08:00
Sebastien Bourdeauducq
db62cf2abe
wrpll: convert tests to self-checking unittests
2020-10-08 18:38:01 +08:00
Sebastien Bourdeauducq
07d43b6e5f
wrpll: babysit Vivado DSP retiming
...
Design now passes timing.
2020-10-08 17:51:27 +08:00
Sebastien Bourdeauducq
7dfb4af682
kasli2: work around vivado clock constraint problem
2020-10-08 16:31:39 +08:00
Sebastien Bourdeauducq
96a5df0dc6
kasli2: add false path constraint for wrpll helper clock
2020-10-08 16:19:44 +08:00
Sebastien Bourdeauducq
6248970ef8
wrpll: clean up matlab comparison test
2020-10-08 15:40:15 +08:00
hartytp
cd8c2ce713
wrpll: add test to compare collector+filter against Matlab simulation
2020-10-08 15:36:56 +08:00
hartytp
d780faf4ac
wrpll.si549: initialize the clock divider to a sensible value
2020-10-08 15:32:27 +08:00
hartytp
7d7be6e711
wrpll.core: move collector into helper CD so we can get tags out while the filters are reset
2020-10-08 15:32:27 +08:00
Sebastien Bourdeauducq
3fa5d0b963
wrpll: clean up sign extension
2020-10-08 15:32:27 +08:00
hartytp
87911810d6
wrpll.core: add CSRs to monitor the collector outputs
2020-10-08 15:32:27 +08:00
hartytp
f2f942a8b4
wrpll.ddmtd: remove CSRs from DDMTD
...
We will gather then from the collector output so we can get all tags on the same cycle
2020-10-08 15:32:27 +08:00
hartytp
85bb641917
wrpll.ddmtd: fix first edge deglitcher
...
The blind counter should be held in reset whenever the input is high,
not just when there is a rising edge (otherwise the counter runs down
during the main pulse and can then re-trigger on jitter from the falling edge)
2020-10-08 15:32:27 +08:00
hartytp
f3cd0fc675
wrpll.filters: the helper clipping threshold is currently way too low. Move clipping after the bitshift to increase a bit.
...
TODO: think about this and pick a sensible threshold (and also think about integrator anti windup)
2020-10-08 15:32:27 +08:00
hartytp
e5e648bde1
wrpll: add bit shift for collector helper output
2020-10-08 15:32:27 +08:00
hartytp
c9ae406ac6
wrpll: change the DDMTD helper frequency to match CERN, improve docs
2020-10-08 15:32:27 +08:00
hartytp
f6f6045f1a
wrpll.thls: fix make
2020-10-08 15:32:27 +08:00
hartytp
b44b870452
wrpll.filters: update to match Weida's MatLab simulations
2020-10-08 15:32:27 +08:00
hartytp
e9ab434fa7
wrpll.core: update for modified collector
2020-10-08 15:32:27 +08:00
Sebastien Bourdeauducq
17c952b8fb
wrpll: style
2020-10-08 15:32:27 +08:00
hartytp
ebb7ccbfd1
wrpll: document DDMTD collector and fix unwrapping
2020-10-08 15:32:27 +08:00
Robert Jördens
50b4eb4840
Merge branch 'master' into phaser
...
* master: (26 commits)
fastino: documentation and eem pass-through
kasli2: forward sma_clkin to si5324
test: relax test_dma_playback_time on Zynq
rpc: fixed _write_bool
fastino: document/cleanup
build_soc: remove assertion that was used for test runs
metlino_sayma_ttl: Fix RTIO frequency & demo code (#1516 )
Revert "test: temporarily disable test_async_throughput"
build_soc: rename identifier_str to gateware_identifier_str
test: relax loopback gate timing
test: temporarily disable test_async_throughput
test: relax test_pulse_rate on Zynq
test: skip NonexistentI2CBus if I2C is not supported
build_soc: override identifier_str only for gateware
examples: add Metlino master, Sayma satellite with TTLOuts via FMC
sayma_amc: add support for 4x DIO output channels via FMC
fmcdio_vhdci_eem: fix pin naming
build_soc: add identifier_str override option
RPC: optimization by caching
test: improved test_performance
...
2020-09-22 16:02:25 +00:00
Robert Jördens
c55f2222dc
fastino: documentation and eem pass-through
...
* Repeat information about matching log2_width a few times
in the hope that people read it. #1518
* Pass through log2_width in kasli_generic json. close #1481
* Check DAC value range. #1518
2020-09-22 17:58:53 +02:00
Sebastien Bourdeauducq
29c940f4e3
kasli2: forward sma_clkin to si5324
2020-09-17 16:53:43 +08:00
Robert Jördens
868a9a1f0c
phaser: new multidds
2020-09-16 14:06:38 +00:00
Robert Jördens
c18f515bf9
phaser: rework rtio channels, sync_dly, init()
2020-09-16 12:23:07 +00:00
Robert Jördens
fdd2d6f2fb
phaser: SI methods
2020-09-12 11:02:37 +00:00
Robert Jördens
4e24700205
phaser: spelling
2020-09-09 16:52:52 +00:00
Robert Jördens
8aaeaa604e
phaser: share_lut
2020-09-07 16:06:35 +00:00
Astro
002a71dd8d
build_soc: rename identifier_str to gateware_identifier_str
2020-09-02 00:00:57 +08:00
Harry Ho
dfbf3311cb
sayma_amc: add support for 4x DIO output channels via FMC
2020-08-31 16:21:45 +08:00
Harry Ho
1ad9deaf91
fmcdio_vhdci_eem: fix pin naming
2020-08-31 16:21:45 +08:00
Astro
45ae6202c0
build_soc: add identifier_str override option
...
Signed-off-by: Stephan Maka <stephan@spaceboyz.net>
2020-08-31 11:48:58 +08:00
Robert Jördens
272dc5d36a
phaser: documentation
2020-08-28 16:36:44 +00:00
Robert Jördens
96fc248d7c
phaser: synchronize multidds to frame
2020-08-27 14:28:19 +00:00
Robert Jördens
c10ac2c92a
phaser: add trf, duc, interfaces, redo body assembly, use more natrual iq ordering (i lsb)
2020-08-27 14:26:09 +00:00
Robert Jördens
e5e2392240
phaser: wire up multidds
2020-08-26 17:12:41 +00:00
Robert Jördens
d1be1212ab
phaser: coredevice shim, dds [wip]
2020-08-26 15:10:50 +00:00
Robert Jördens
20fcfd95e9
phaser: coredevice shim, readback fix
2020-08-24 15:46:31 +00:00
Robert Jördens
bcefb06e19
phaser: ddb template, split crc
2020-08-24 14:51:50 +00:00
Robert Jördens
11c9def589
phaser: readback delay, test fastlink
2020-08-24 14:49:36 +00:00
Robert Jördens
63e4b95325
fastlink: rework crc injection
2020-08-23 19:41:13 +00:00
Robert Jördens
a27a03ab3c
fastlink: fix crc vs data width
2020-08-23 19:02:50 +00:00
Robert Jördens
7e584d0da1
fastino: use fastlink
2020-08-22 11:56:23 +00:00
Robert Jördens
3e99f1ce5a
phaser: refactor link
2020-08-22 11:56:23 +00:00
Robert Jördens
a34a647ec4
phaser: refactor fastlink
2020-08-22 11:56:23 +00:00
Robert Jördens
aa0154d8e2
phaser: initial
2020-08-22 11:56:23 +00:00
Sebastien Bourdeauducq
504f72a02c
rtio: remove legacy i_overflow_reset CSR
2020-08-06 17:52:32 +08:00
cw-mlabs
e4b16428f5
wrpll: fix run signal
2020-07-27 13:02:02 +08:00
cw-mlabs
8dd9a6d024
wrpll: fix scl signal
2020-07-27 12:59:32 +08:00
Sebastien Bourdeauducq
4340a5cfc1
rtio/dma: fix previous commit
2020-07-12 10:14:22 +08:00
Sebastien Bourdeauducq
f2e0d27334
rtio/dma: remove dead/broken code
2020-07-12 10:13:18 +08:00
Sebastien Bourdeauducq
901be75ba4
sayma_rtm: fix Si5324 reset
...
Closes #1483
2020-07-11 09:51:01 +08:00
Sebastien Bourdeauducq
2d1f1fff7f
kasli_generic: do not attempt to use SFP LED for RTIO on 2.0+
2020-07-08 18:14:44 +08:00
Sebastien Bourdeauducq
cb76f9da89
metlino: fix CSR collisions
...
Closes #1425
2020-05-29 15:59:44 +08:00
Sebastien Bourdeauducq
bd9eec15c0
metlino: increase number of DRTIO links
...
Seems OK with Vivado 2019.2.
2020-05-29 15:59:16 +08:00
Sebastien Bourdeauducq
d8b5bcf019
sayma_amc: support uTCA backplane for DRTIO
2020-05-29 14:58:49 +08:00
Sebastien Bourdeauducq
8b939b7cb3
sayma_amc: remove Master (obsoleted by Metlino)
2020-05-29 14:40:49 +08:00
Sebastien Bourdeauducq
4e9a529e5a
kasli: integrate WRPLL
2020-05-07 21:34:02 +08:00
Sebastien Bourdeauducq
60e5f1c18e
kasli: DRTIO support for Kasli 2
2020-05-07 20:09:43 +08:00
Sebastien Bourdeauducq
1f2182d4c7
kasli: default to hardware v2
2020-05-07 19:15:03 +08:00
Sebastien Bourdeauducq
b83afedf43
kasli: light up ERROR LED on panic
2020-05-07 19:06:10 +08:00
Sebastien Bourdeauducq
7e400a78f4
kasli: compile tester for hw 2.0 by default
2020-04-28 16:07:56 +08:00
Sebastien Bourdeauducq
3a7819704a
rtio: support direct 64-bit now CSR in KernelInitiator
2020-04-26 16:04:32 +08:00
Sebastien Bourdeauducq
d19f28fa84
kasli: v2 clocking WIP, remove SFP LEDs from RTIO
2020-04-23 23:02:18 +08:00
Robert Jördens
ea79ba4622
ttl_serdes: detect edges on short pulses
...
Edges on pulses shorter than the RTIO period were missed because the
reference sample and the last sample of the serdes word are the same.
This change enables detection of edges on pulses as short as the
serdes UI (and shorter as long as the pulse still hits a serdes sample
aperture).
In any RTIO period, only the leading event corresponding to the first
edge with slope according to sensitivity is registerd. If the channel is
sensitive to both rising and falling edges and if the pulse is contained
within an RTIO period, or if it is sensitive only to one edge slope and
there are multiple pulses in an RTIO period, only the leading event is
seen. Thus this possibility of lost events is still there. Only the
conditions under which loss occurs are reduced.
In testing with the kasli-ptb6 variant, this also improves resource
usage (a couple hundred LUT) and timing (0.1 ns WNS).
2020-04-13 13:21:03 +02:00
Sebastien Bourdeauducq
ec7b2bea12
sayma: round FTW like Urukul in JDCGSyncDDS
2020-04-08 15:00:33 +08:00
Sebastien Bourdeauducq
0f4be22274
sayma: add simple sychronized DDS for testing
2020-04-08 14:13:54 +08:00
Sebastien Bourdeauducq
61d4614b61
sayma: fix/cleanup DRTIO-DAC sync interaction
2020-04-06 22:34:05 +08:00
Sebastien Bourdeauducq
ffd3172e02
sayma: move SYSREF DDMTD to RTM ( #795 )
2020-04-06 00:01:28 +08:00
Robert Jördens
e803830b3b
fastino: support wide RTIO interface and channel groups
2020-03-05 17:55:04 +00:00
Sebastien Bourdeauducq
6d26def3ce
sayma: drive filtered_clk_sel on master variant
2020-02-06 22:28:49 +08:00
Sebastien Bourdeauducq
c7de1f2e6b
metlino: drive clock muxes
2020-02-05 00:06:34 +08:00
Sebastien Bourdeauducq
dfa033eb87
wrpll: new collector from Weida/Tom
2020-01-24 10:31:52 +08:00
Sebastien Bourdeauducq
dee16edb78
wrpll: DDMTD sampler double latching
2020-01-22 19:16:26 +08:00
Robert Jördens
248230a89e
fastino: style
2020-01-20 13:25:00 +01:00
Robert Jördens
2c4e5bfee4
fastino: add [WIP]
2020-01-20 13:25:00 +01:00
Robert Jördens
01a6e77d89
mirny: add
...
* This targets unrelease CPLD gateware (https://github.com/quartiq/mirny/issues/1 )
* includes initial coredevice driver, eem shims, and kasli_generic tooling
* addresses the ARTIQ side of #1130
* Register abstraction to be written
Signed-off-by: Robert Jördens <rj@quartiq.de>
2020-01-20 13:13:08 +01:00
Sebastien Bourdeauducq
6c3e71a83a
wrpll: cleanup
2020-01-18 09:43:43 +08:00
Sebastien Bourdeauducq
344f8bd12a
wrpll: collector patch from Weida
2020-01-18 09:42:58 +08:00
Sebastien Bourdeauducq
6c948c7726
sayma: RF switch control is active-low on Basemod, invert
2020-01-16 08:59:52 +08:00
Sebastien Bourdeauducq
50302d57c0
wrpll: more careful I2C timing
2020-01-14 20:03:46 +08:00
Sebastien Bourdeauducq
105dd60c78
wrpll: ADPLLProgrammer mini test bench and fixes
2020-01-14 16:52:25 +08:00
Sebastien Bourdeauducq
3242e9ec6c
wrpll: loop test
2020-01-13 22:31:57 +08:00
Sebastien Bourdeauducq
8ec0f2e717
wrpll: implement ADPLLProgrammer
2020-01-13 22:30:11 +08:00
Sebastien Bourdeauducq
d685619bcd
wrpll: collector code modifications from Weida
2020-01-13 20:42:41 +08:00
Sebastien Bourdeauducq
a666766f38
wrpll: add ADPLL offset registers
2019-12-30 22:19:42 +08:00
Sebastien Bourdeauducq
5c6e394928
ddmtd: add collector
2019-12-30 22:17:44 +08:00
Sebastien Bourdeauducq
f57f235dca
wrpll: new frequency meter
...
As per Mattermost discussion with Tom.
2019-12-30 19:47:57 +08:00
Sebastien Bourdeauducq
9e15ff7e6a
wrpll: improve DDMTD deglitcher
2019-12-30 16:56:06 +08:00
Sebastien Bourdeauducq
b7f1623197
sayma_rtm: connect attenuator shift registers in series
2019-12-20 18:58:31 +08:00
Sebastien Bourdeauducq
1c9cbe6285
sayma_rtm: add basemod attenuators on RTIO
2019-12-20 15:25:55 +08:00
Sebastien Bourdeauducq
6ee15fbcae
sayma_rtm: basemod RF switches
2019-12-18 10:33:29 +08:00
Sebastien Bourdeauducq
52112d54f9
kasli_generic: expose peripheral_processors dictionary. Closes #1403
2019-12-10 10:30:06 +08:00
Sebastien Bourdeauducq
150a02117c
sayma_rtm: drive clk_src_ext_sel
2019-12-09 19:47:50 +08:00
Sebastien Bourdeauducq
307a6ca140
gth_ultrascale: make OBUFDS_GTE3 work
...
https://www.xilinx.com/support/answers/67919.html
2019-12-09 18:13:22 +08:00
Sebastien Bourdeauducq
2b5213b013
wrpll: constrain clocks
2019-12-09 12:26:44 +08:00
Sebastien Bourdeauducq
05e2e1899a
wrpll: update OBUFDS_GTE2 comment
...
Seems O can fan out simultaneously to transceiver and fabric.
Kasli is using ODIV2 for no particular reason.
2019-12-09 11:58:54 +08:00
Sebastien Bourdeauducq
4148efd2ee
wrpll: implement filters and connect to Si549
2019-12-09 11:47:29 +08:00
Sebastien Bourdeauducq
d43fe644f0
wrpll: stabilize DDMTDSamplerGTP
2019-12-09 11:47:14 +08:00
Sebastien Bourdeauducq
0499f83580
wrpll: helper clock sanity check
2019-12-08 23:46:33 +08:00
Sebastien Bourdeauducq
46a776d06e
sayma: introduce WRPLL on RTM
2019-12-08 15:30:00 +08:00
Sebastien Bourdeauducq
883310d83e
sayma_rtm: si5324 -> cdrclkc
2019-12-08 14:26:05 +08:00
Sebastien Bourdeauducq
57a5bea43a
sayma_rtm: support setting RTIO frequency
2019-12-08 11:45:31 +08:00
Sebastien Bourdeauducq
da9237de53
wrpll: support differential DDMTD inputs
2019-12-07 18:18:57 +08:00
Sebastien Bourdeauducq
7098854b0f
wrpll: share DDMTD counter
2019-12-04 19:05:56 +08:00
Robert Jördens
05c5fed07d
suservo: stray comma
2019-12-03 08:38:07 +00:00
Robert Jördens
56074cfffa
suservo: support operating with one urukul
...
implemented by wiring up the second Urukul to dummy pins
Signed-off-by: Robert Jördens <rj@quartiq.de>
2019-12-02 11:30:20 +01:00
Robert Jördens
86e1924493
kasli_generic: support external reference on masters
2019-11-30 07:34:41 +00:00
Sebastien Bourdeauducq
eb271f383b
wrpll: add DDMTD cores
2019-11-28 22:03:50 +08:00
Sebastien Bourdeauducq
2e55e39ac7
wrpll: use spaces to indent
2019-11-28 17:40:25 +08:00
Sebastien Bourdeauducq
354d82cfe3
wrpll: drive helper clock domain
2019-11-28 17:40:00 +08:00
Sebastien Bourdeauducq
68cab5be8c
si549: cleanups
2019-11-28 16:36:59 +08:00
Sebastien Bourdeauducq
4832bfb08c
wrpll: i2c functions, select_recovered_clock placeholder
2019-11-27 21:21:00 +08:00
Sebastien Bourdeauducq
c536f6c4df
sayma_amc: output ddmtd_rec_clk
2019-11-20 19:16:04 +08:00
Sebastien Bourdeauducq
ae50da09c4
drtio/gth_ultrascale: support OBUFDS_GTE3
2019-11-20 19:15:50 +08:00
Sebastien Bourdeauducq
fe0c324b38
sayma: integrate si549 core
2019-11-20 17:37:16 +08:00
Sebastien Bourdeauducq
fa41c946ea
wrpll: si549 fixes
2019-11-20 17:04:24 +08:00
Sebastien Bourdeauducq
c5dbab1929
gateware: move wrpll to drtio
2019-11-20 14:43:08 +08:00
David Nadlinger
bc3b55b1a8
gateware/eem: Force IOB=TRUE on Urukul SYNC output
...
Without this, the final register in the SYNC signal TTLClockGen
isn't (always) placed in the I/O tile, leading to more jitter
than necessary, and causing "double window" artefacts. See
sinara-hw/Urukul#16 for more details.
(Patch based on work by Weida Zhang, testing by various members
of the community in Oxford and elsewhere.)
2019-11-05 17:14:07 +08:00
Sebastien Bourdeauducq
98854473dd
sayma_amc: use all transceivers on master ( #1230 )
2019-11-02 12:12:32 +08:00
Sebastien Bourdeauducq
42af76326f
kasli: enlarge integrated CPU SRAM for DRTIO masters
...
Required by the bootloader netboot support.
2019-11-01 10:15:13 +08:00
Sebastien Bourdeauducq
228e44a059
sayma: enable Ethernet on DRTIO satellite variant
...
So that netboot can be used in bootloader.
2019-10-30 21:39:00 +08:00
Sebastien Bourdeauducq
dc71039934
sayma, metlino: increase integrated_sram_size on Ethernet-enabled variants
2019-10-30 21:36:00 +08:00
Sebastien Bourdeauducq
462cf5967e
bootloader: add netboot support
2019-10-30 21:23:42 +08:00
Sebastien Bourdeauducq
8fa3c6460e
sayma_amc: set direction of external TTL buffer according to RTIO PHY OE
2019-10-16 18:48:50 +08:00
Sebastien Bourdeauducq
37d0a5dc19
rtio/ttl: expose OE
2019-10-16 18:48:20 +08:00
Sebastien Bourdeauducq
bc060b7f01
style
2019-10-16 18:18:11 +08:00
Sebastien Bourdeauducq
21a1c6de3f
sayma: use SFP0 for DRTIO master
2019-10-16 17:53:40 +08:00
Sebastien Bourdeauducq
314d9b5d06
kasli: default to 125MHz frequency for DRTIO
...
This is the consistent and most common option. Sayma will also eventually move to it.
2019-10-08 12:59:52 +08:00
Sebastien Bourdeauducq
4df2c5d1fb
sayma: prepare for SYSREF align
...
We will try DDMTD on the AMC first, as this is simpler and perhaps will work on v2 after the power supply fixes.
2019-10-08 12:30:47 +08:00
Sebastien Bourdeauducq
03007b896e
sayma_amc: sma -> mcx
2019-10-07 20:31:35 +08:00
Sebastien Bourdeauducq
97a0dee3e8
jesd204: remove ibuf_disable
...
We use the MOSFET to mute the HMC7043 noise on hardware v2 instead.
2019-10-06 22:26:31 +08:00
Sebastien Bourdeauducq
f8e4cc37d0
sayma_rtm: reset and detect DACs
2019-10-06 20:15:27 +08:00
Sebastien Bourdeauducq
f62dc7e1d4
sayma: refactor JESD DAC channel groups
2019-10-06 20:15:09 +08:00
Sebastien Bourdeauducq
1c6c22fde9
sayma_amc: HMC830_REF moved to RTM side
2019-10-06 18:15:37 +08:00
Sebastien Bourdeauducq
e6ff44301b
sayma_amc: cleanup (v2.0 only)
2019-10-06 18:11:43 +08:00
Sebastien Bourdeauducq
e9b81f6e33
remove serwb
...
DRTIO is a better solution
2019-10-06 18:10:23 +08:00
Sebastien Bourdeauducq
7cd02d30b7
sayma_rtm_drtio: replace sayma_rtm
2019-10-06 17:59:53 +08:00
Sebastien Bourdeauducq
b3b85135a3
sayma_rtm_drtio: add DDMTD core, move specific cores out of SatelliteBase
2019-10-06 17:59:11 +08:00
Sebastien Bourdeauducq
346c985347
sayma_rtm_drtio: use artiq_sayma folder
2019-10-06 17:30:08 +08:00
Sebastien Bourdeauducq
4198033657
sayma_rtm_drtio: cleanup (v2.0 only)
2019-10-06 16:42:34 +08:00
Sebastien Bourdeauducq
5612b31860
sayma_rtm_drtio: add HMC clock chip and DAC control
2019-10-06 16:15:24 +08:00
Sebastien Bourdeauducq
a8cf4c2b18
sayma_rtm: hwrev v2.0 by default
2019-10-06 13:25:30 +08:00
Sebastien Bourdeauducq
bb5ff46f7d
Merge branch 'wrpll'
2019-10-05 10:24:11 +08:00
Sebastien Bourdeauducq
7b95814cf5
sayma_amc: refactor, add SimpleSatellite variant
2019-10-05 10:24:06 +08:00
Sebastien Bourdeauducq
58b7bdcecc
sayma_amc: refactor RTM FPGA code
2019-10-05 10:24:06 +08:00
Sebastien Bourdeauducq
96fc4a21e8
sayma_amc: remove dummy FPGA pin assignment testing code
2019-10-05 10:24:06 +08:00
Sebastien Bourdeauducq
6aa68e1715
sayma_rtm2: select filtered clock from Si5324
2019-10-04 22:56:16 +08:00
Sebastien Bourdeauducq
6cb0f5de59
sayma_amc: enable DRTIO switching
2019-10-04 22:55:23 +08:00
Sebastien Bourdeauducq
0cf8a46bbd
sayma_amc2: select filtered clock from Si5324
2019-10-04 21:28:26 +08:00
Robert Jördens
f0e87d2e59
grabber: remove unused code
2019-09-20 15:26:12 +02:00
Sebastien Bourdeauducq
991c686d72
kasli_generic,eem: print RTIO channels in hex like artiq_ddb_template
2019-09-11 15:51:53 +08:00
Sebastien Bourdeauducq
7492a59f6d
kasli_generic: add SUServo support ( #1343 )
2019-09-11 11:12:48 +08:00
Sebastien Bourdeauducq
21021beb08
kasli: remove opticlock (moved to kasli_generic)
2019-09-09 15:03:10 +08:00
Sebastien Bourdeauducq
cfb5ef5548
kasli_generic: add Novogorny support
2019-09-09 14:54:34 +08:00
Sebastien Bourdeauducq
1fb317778a
eem/grabber: allow third EEM to be specified
2019-08-29 18:58:12 +08:00
Sebastien Bourdeauducq
959679d8b7
wrpll: add I2CMasterMachine
2019-08-27 18:02:05 +08:00
Sebastien Bourdeauducq
1fd2322662
wrpll/thls: implement global writeback
2019-08-15 23:16:17 +08:00
Sebastien Bourdeauducq
24082b687e
wrpll/filters: clean up and make compatible with thls
2019-08-15 17:58:22 +08:00
Sebastien Bourdeauducq
9331fafab0
wrpll/filters: new code from Weida
2019-08-15 17:24:40 +08:00
Sebastien Bourdeauducq
5c3974c265
wrpll/thls: fix opcode decoding
2019-08-15 17:12:48 +08:00
Sebastien Bourdeauducq
19620948bf
wrpll/thls: implement signed numbers
2019-08-15 17:04:17 +08:00
Sebastien Bourdeauducq
efc43142a6
wrpll/thls: implement min/max
2019-08-15 16:42:59 +08:00
Sebastien Bourdeauducq
44969b03ad
wrpll/thls: rework instruction decoding
2019-08-15 15:55:13 +08:00
Sebastien Bourdeauducq
2776c5b16b
wrpll/thls: support mulshift
2019-08-15 15:07:13 +08:00
Sebastien Bourdeauducq
f861459ace
wrpll: add filter algorithms (WIP)
2019-08-02 13:23:16 +08:00
Sebastien Bourdeauducq
7a5dcbe60e
wrpll/thls: support processor start/stop
2019-07-24 18:51:33 +08:00
Sebastien Bourdeauducq
623446f82c
wrpll/thls: simple simulation demo
2019-07-20 18:50:57 +08:00
Sebastien Bourdeauducq
831b3514d3
wrpll/thls: stop at return statement
2019-07-19 16:27:29 +08:00
Sebastien Bourdeauducq
34222b3f38
wrpll: encode thls program
2019-07-09 17:56:14 +08:00
Sebastien Bourdeauducq
5f461d08cd
wrpll: add simple thls compiler
2019-07-09 16:07:31 +08:00
Sebastien Bourdeauducq
e4fff390a8
si590 -> si549
...
Had mistaken the part numbers.
2019-07-07 09:39:55 +08:00
Sebastien Bourdeauducq
dceb5ae501
wrpll: Si590 I2C mux, CDC
2019-07-05 23:42:37 +08:00
Sebastien Bourdeauducq
f8dba7ae35
rtio: use BlindTransfer from Migen
2019-07-05 18:46:18 +08:00
David Nadlinger
0353966ef7
gateware/suservo: Sign-extend data on RTIO read-back
...
See GitHub #1327 for original patch by Brad Bondurant.
2019-06-14 23:46:16 +01:00
David Nadlinger
720838a23e
gateware/suservo: Avoid magic number for activation delay width
...
Mostly for documentation purposes; 8 bits ought to be enough for
everyone.
2019-06-14 23:45:40 +01:00
Sebastien Bourdeauducq
43e58c939c
sayma: drop MasterDAC
...
This seemed like a good idea then, but it introduces complexity, corner cases, and additional testing difficulties.
Now Sayma works fine with Kasli as a master, which is simpler.
2019-06-14 14:06:16 +08:00
Sebastien Bourdeauducq
b04e15741b
drop SI5324_SAYMA_REF
2019-06-14 14:03:48 +08:00
Sebastien Bourdeauducq
bc2cfd77f5
metlino: add EEMs
2019-05-19 18:16:00 +08:00
Sebastien Bourdeauducq
cdef50c0dd
sayma_amc: Urukul v1.3
2019-05-19 16:54:38 +08:00
Sebastien Bourdeauducq
9dcaae6395
metlino: use variant output directory
2019-05-19 16:24:51 +08:00
Sebastien Bourdeauducq
b4779969d0
metlino: work around vivado bug ( #1230 )
2019-05-19 11:27:27 +08:00
Sebastien Bourdeauducq
874542f33f
add Metlino support
2019-05-19 10:57:43 +08:00
hartytp
cfe1f56f73
suservo: add some more comments to the RTServoMem to clarify the RTIO interface ( #1323 )
2019-05-17 16:12:35 +01:00
Sebastien Bourdeauducq
fda3cb2482
kasli_generic: add edge counter support
2019-05-09 17:19:11 +08:00
Robert Jördens
ead9a42842
kasli: remove VLBAIMaster, VLBAISatellite variants
2019-05-08 15:58:25 +00:00
Robert Jördens
0c9b810501
kasli: remove PTB/PTB2/LUH/HUB variants
...
see sinara-systems and nix-scripts repos
2019-05-08 15:51:18 +00:00
Robert Jördens
1d2cc60e0d
kasli_generic: support ext_ref
2019-05-08 15:51:18 +00:00
David Nadlinger
4d215cf541
firmware: Add Si5324 config for 125 MHz ext ref
...
PLL divider settings as suggested by DSPLLsim 5.1.
2019-04-15 22:22:19 +01:00
Sebastien Bourdeauducq
97b7ed557b
sayma_amc: do not use SFP0 (now used for Ethernet)
2019-04-12 18:47:18 +08:00
Chris Ballance
4499ef1748
kasli: only add moninj core if there are probes to monitor
2019-03-24 14:09:52 +08:00