forked from M-Labs/artiq
wrpll: clean up sign extension
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parent
87911810d6
commit
3fa5d0b963
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@ -8,13 +8,6 @@ from artiq.gateware.drtio.wrpll.ddmtd import DDMTD, Collector
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from artiq.gateware.drtio.wrpll import thls, filters
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def _eq_sign_extend(t, s):
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"""Assign target signal `t` from source `s`, sign-extending `s` to the
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full width.
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"""
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return t.eq(Cat(s, Replicate(s[-1], len(t) - len(s))))
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class FrequencyCounter(Module, AutoCSR):
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def __init__(self, timer_width=23, counter_width=23, domains=["helper", "rtio", "rtio_rx0"]):
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for domain in domains:
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@ -68,6 +61,13 @@ class WRPLL(Module, AutoCSR):
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self.ref_tag = CSRStatus(N)
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self.main_tag = CSRStatus(N)
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main_diff_tag_32 = Signal((32, True))
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helper_diff_tag_32 = Signal((32, True))
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self.comb += [
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self.main_diff_tag.status.eq(main_diff_tag_32),
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self.helper_diff_tag.status.eq(helper_diff_tag_32)
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]
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self.clock_domains.cd_helper = ClockDomain()
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self.clock_domains.cd_filter = ClockDomain()
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self.helper_reset.storage.attr.add("no_retiming")
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@ -126,8 +126,8 @@ class WRPLL(Module, AutoCSR):
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If(collector_stb_sys,
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self.tag_arm.w.eq(0),
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If(self.tag_arm.w,
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_eq_sign_extend(self.main_diff_tag.status, main_diff_tag_sys),
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_eq_sign_extend(self.helper_diff_tag.status, helper_diff_tag_sys),
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main_diff_tag_32.eq(main_diff_tag_sys),
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helper_diff_tag_32.eq(helper_diff_tag_sys),
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self.ref_tag.status.eq(ref_tag_sys),
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self.main_tag.status.eq(main_tag_sys)
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)
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