forked from M-Labs/artiq
fastino: documentation and eem pass-through
* Repeat information about matching log2_width a few times in the hope that people read it. #1518 * Pass through log2_width in kasli_generic json. close #1481 * Check DAC value range. #1518
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@ -19,17 +19,17 @@ class Fastino:
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bit using :meth:`set_update`. Update is self-clearing. This enables atomic
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DAC updates synchronized to a frame edge.
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The `log2_width=0` RTIO layout uses one DAC channel per RTIO address
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and a dense RTIO address space. The RTIO words are narrow.
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(32 bit compared to 512) and few-channel updates are efficient.
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There is the least amount of DAC state tracking in kernels,
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at the cost of more DMA and RTIO data.
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The `log2_width=0` RTIO layout uses one DAC channel per RTIO address and a
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dense RTIO address space. The RTIO words are narrow. (32 bit) and
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few-channel updates are efficient. There is the least amount of DAC state
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tracking in kernels, at the cost of more DMA and RTIO data.
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The setting here and in the RTIO PHY (gateware) must match.
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Other `log2_width` (up to `log2_width=5`) settings pack multiple
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(in powers of two) DAC channels into one group and into one RTIO write.
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The RTIO data width increases accordingly. The `log2_width`
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LSBs of the RTIO address for a DAC channel write must be zero and the
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address space is sparse.
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address space is sparse. For `log2_width=5` the RTIO data is 512 bit wide.
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If `log2_width` is zero, the :meth:`set_dac`/:meth:`set_dac_mu` interface
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must be used. If non-zero, the :meth:`set_group`/:meth:`set_group_mu`
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@ -37,9 +37,8 @@ class Fastino:
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:param channel: RTIO channel number
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:param core_device: Core device name (default: "core")
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:param log2_width: Width of DAC channel group (power of two,
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see the RTIO PHY for details). Value must match the corresponding value
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in the RTIO PHY.
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:param log2_width: Width of DAC channel group (logarithm base 2).
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Value must match the corresponding value in the RTIO PHY (gateware).
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"""
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kernel_invariants = {"core", "channel", "width"}
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@ -113,7 +112,10 @@ class Fastino:
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:param voltage: Voltage in SI Volts.
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:return: DAC data word in machine units, 16 bit integer.
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"""
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return (int(round((0x8000/10.)*voltage)) + 0x8000) & 0xffff
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data = int(round((0x8000/10.)*voltage)) + 0x8000
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if data < 0 or data > 0xffff:
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raise ValueError("DAC voltage out of bounds")
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return data
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@portable
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def voltage_group_to_mu(self, voltage, data):
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@ -618,11 +618,11 @@ class Fastino(_EEM):
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) for pol in "pn"]
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@classmethod
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def add_std(cls, target, eem, iostandard="LVDS_25"):
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def add_std(cls, target, eem, log2_width, iostandard="LVDS_25"):
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cls.add_extension(target, eem, iostandard=iostandard)
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phy = fastino.Fastino(target.platform.request("fastino{}_ser_p".format(eem)),
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target.platform.request("fastino{}_ser_n".format(eem)),
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log2_width=0)
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log2_width=log2_width)
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target.submodules += phy
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target.rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=4))
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@ -109,7 +109,8 @@ def peripheral_mirny(module, peripheral):
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def peripheral_fastino(module, peripheral):
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if len(peripheral["ports"]) != 1:
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raise ValueError("wrong number of ports")
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eem.Fastino.add_std(module, peripheral["ports"][0])
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eem.Fastino.add_std(module, peripheral["ports"][0],
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peripheral.get("log2_width", 0))
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peripheral_processors = {
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