forked from M-Labs/artiq
wrpll: fix mulshift
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@ -552,7 +552,8 @@ class ProcessorImpl(Module):
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if pd.multiplier_shifts:
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if len(pd.multiplier_shifts) != 1:
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raise NotImplementedError
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multiplier = OpUnit(lambda a, b: a * b >> pd.multiplier_shifts[0],
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# work around Migen's mishandling of Verilog's cretinous operator width rules
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multiplier = OpUnit(lambda a, b: Cat(a, C(0, pd.data_width)) * Cat(b, C(0, pd.data_width)) >> pd.multiplier_shifts[0],
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pd.data_width, pd.multiplier_stages)
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else:
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multiplier = NopUnit(pd.data_width)
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