forked from M-Labs/artiq
wrpll: add bit shift for collector helper output
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@ -94,7 +94,7 @@ class WRPLL(Module, AutoCSR):
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]
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self.comb += [
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self.filter_helper.input.eq(self.collector.out_helper),
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self.filter_helper.input.eq(self.collector.out_helper << 22),
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self.filter_helper.input_stb.eq(self.collector.out_stb),
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self.filter_main.input.eq(self.collector.out_main),
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self.filter_main.input_stb.eq(self.collector.out_stb)
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