forked from M-Labs/artiq
fastlink: rework crc injection
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@ -23,7 +23,7 @@ class SerDes(Module):
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* `n_crc` CRC bits per frame for divisor poly `poly`
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"""
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# pins
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self.data = [Signal(2) for _ in range(n_data)]
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self.data = [Signal(2, reset_less=True) for _ in range(n_data)]
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n_mosi = n_data - 2 # mosi lanes
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n_word = n_mosi*t_clk # bits per word
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t_frame = t_clk*n_frame # frame duration
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@ -48,6 +48,7 @@ class SerDes(Module):
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# build from LSB to MSB because MSB first
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for i in range(n_frame): # iterate over words
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if i == 0: # data and checksum
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words_.append(C(0, n_crc))
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k = n_word - n_crc
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elif i == 1: # marker
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words_.append(C(1))
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@ -61,30 +62,31 @@ class SerDes(Module):
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words_.append(self.payload[j:j + k])
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j += k
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words_ = Cat(words_)
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assert len(words_) == n_frame*n_word - n_crc
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assert len(words_) == n_frame*n_word
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words = Signal(len(words_))
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self.comb += words.eq(words_)
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clk = Signal(t_clk, reset=d_clk)
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i = Signal(max=t_frame//2)
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# big shift register for clk and mosi
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sr = [Signal(t_frame - n_crc//n_mosi, reset_less=True)
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for i in range(n_mosi)]
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# big shift register for mosi and
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sr = [Signal(t_frame, reset_less=True) for i in range(n_mosi)]
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assert len(Cat(sr)) == len(words)
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# DDR bits for each register
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crc_data = [sri[-2] for sri in sr] + [sri[-1] for sri in sr]
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sr_t = [sr[i % n_mosi][i//n_mosi] for i in range(len(words))]
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data_t = ([d[0] for d in self.data[:-1]] +
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[d[1] for d in self.data[:-1]])
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miso_sr = Signal(t_frame, reset_less=True)
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miso_sr_next = Signal.like(miso_sr)
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self.comb += [
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self.stb.eq(i == t_frame//2 - 1),
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# LiteETHMACCRCEngine takes data LSB first
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self.crc.data.eq(Cat(reversed(crc_data))),
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self.crc.data.eq(Cat(reversed(sr_t[-2*n_mosi:]))),
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miso_sr_next.eq(Cat(self.data[-1], miso_sr)),
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[di.eq(sri[-2:]) for di, sri in zip(self.data, [clk] + sr)],
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]
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self.sync.rio_phy += [
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# shift everything by two bits
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[sri.eq(Cat(sri[-2:], sri)) for sri in [clk] + sr],
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[di.eq(sri[-2:]) for di, sri in zip(self.data, [clk] + sr)],
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clk.eq(Cat(clk[-2:], clk)),
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[sri.eq(Cat(C(0, 2), sri)) for sri in sr],
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miso_sr.eq(miso_sr_next),
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self.crc.last.eq(self.crc.next),
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i.eq(i + 1),
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@ -97,10 +99,8 @@ class SerDes(Module):
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# unload miso
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self.readback.eq(Cat([miso_sr_next[t_miso + i*t_clk]
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for i in range(n_frame)])),
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),
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If(i == t_frame//2 - 2,
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# inject crc for the last cycle
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Cat(crc_data[-n_crc:]).eq(self.crc.next),
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Cat(data_t[-n_crc:]).eq(self.crc.next),
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),
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]
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