forked from M-Labs/artiq
wrpll.core: add CSRs to monitor the collector outputs
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@ -8,6 +8,13 @@ from artiq.gateware.drtio.wrpll.ddmtd import DDMTD, Collector
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from artiq.gateware.drtio.wrpll import thls, filters
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def _eq_sign_extend(t, s):
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"""Assign target signal `t` from source `s`, sign-extending `s` to the
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full width.
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"""
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return t.eq(Cat(s, Replicate(s[-1], len(t) - len(s))))
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class FrequencyCounter(Module, AutoCSR):
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def __init__(self, timer_width=23, counter_width=23, domains=["helper", "rtio", "rtio_rx0"]):
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for domain in domains:
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@ -55,6 +62,12 @@ class WRPLL(Module, AutoCSR):
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self.adpll_offset_helper = CSRStorage(24)
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self.adpll_offset_main = CSRStorage(24)
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self.tag_arm = CSR()
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self.main_diff_tag = CSRStatus(32)
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self.helper_diff_tag = CSRStatus(32)
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self.ref_tag = CSRStatus(N)
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self.main_tag = CSRStatus(N)
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self.clock_domains.cd_helper = ClockDomain()
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self.clock_domains.cd_filter = ClockDomain()
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self.helper_reset.storage.attr.add("no_retiming")
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@ -93,6 +106,34 @@ class WRPLL(Module, AutoCSR):
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self.collector.main_stb.eq(self.ddmtd_main.h_tag_update)
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]
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collector_stb_ps = PulseSynchronizer("helper", "sys")
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self.submodules += collector_stb_ps
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self.sync.helper += collector_stb_ps.i.eq(self.collector.out_stb)
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collector_stb_sys = Signal()
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self.sync += collector_stb_sys.eq(collector_stb_ps.o)
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main_diff_tag_sys = Signal((N+2, True))
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helper_diff_tag_sys = Signal((N+2, True))
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ref_tag_sys = Signal(N)
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main_tag_sys = Signal(N)
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self.specials += MultiReg(self.collector.out_main, main_diff_tag_sys)
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self.specials += MultiReg(self.collector.out_helper, helper_diff_tag_sys)
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self.specials += MultiReg(self.collector.tag_ref, ref_tag_sys)
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self.specials += MultiReg(self.collector.tag_main, main_tag_sys)
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self.sync += [
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If(self.tag_arm.re & self.tag_arm.r, self.tag_arm.w.eq(1)),
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If(collector_stb_sys,
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self.tag_arm.w.eq(0),
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If(self.tag_arm.w,
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_eq_sign_extend(self.main_diff_tag.status, main_diff_tag_sys),
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_eq_sign_extend(self.helper_diff_tag.status, helper_diff_tag_sys),
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self.ref_tag.status.eq(ref_tag_sys),
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self.main_tag.status.eq(main_tag_sys)
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)
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)
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]
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self.comb += [
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self.filter_helper.input.eq(self.collector.out_helper << 22),
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self.filter_helper.input_stb.eq(self.collector.out_stb),
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