forked from M-Labs/artiq
phaser: ddb template, split crc
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11c9def589
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bcefb06e19
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@ -485,6 +485,18 @@ class PeripheralManager:
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channel=rtio_offset)
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return 1
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def process_phaser(self, rtio_offset, peripheral):
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self.gen("""
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device_db["{name}"] = {{
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"type": "local",
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"module": "artiq.coredevice.phaser",
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"class": "Phaser",
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"arguments": {{"channel": 0x{channel:06x}}}
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}}""",
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name=self.get_name("phaser"),
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channel=rtio_offset)
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return 2
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def process(self, rtio_offset, peripheral):
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processor = getattr(self, "process_"+str(peripheral["type"]))
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return processor(rtio_offset, peripheral)
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@ -30,6 +30,7 @@ class SerDes(Module):
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n_marker = n_frame//2 + 1
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n_body = n_word*n_frame - n_marker - n_crc
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t_miso = 0 # miso sampling latency TODO
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assert n_crc % n_mosi == 0
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# frame data
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self.payload = Signal(n_body)
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@ -40,8 +41,10 @@ class SerDes(Module):
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# # #
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self.submodules.crc = LiteEthMACCRCEngine(
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data_width=2*n_mosi, width=n_crc, polynom=poly)
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self.submodules.crca = LiteEthMACCRCEngine(
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data_width=n_mosi, width=n_crc, polynom=poly)
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self.submodules.crcb = LiteEthMACCRCEngine(
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data_width=n_mosi, width=n_crc, polynom=poly)
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words_ = []
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j = 0
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@ -71,15 +74,17 @@ class SerDes(Module):
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# big shift register for mosi and
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sr = [Signal(t_frame, reset_less=True) for i in range(n_mosi)]
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assert len(Cat(sr)) == len(words)
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sr_t = [sr[i % n_mosi][i//n_mosi] for i in range(len(words))]
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data_t = ([d[0] for d in self.data[:-1]] +
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[d[1] for d in self.data[:-1]])
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crc_insert = ([d[1] for d in self.data[:-1]] +
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[d[0] for d in self.data[:-1]])
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crc_insert = Cat(crc_insert[-n_crc:])
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miso_sr = Signal(t_frame, reset_less=True)
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miso_sr_next = Signal.like(miso_sr)
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self.comb += [
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self.stb.eq(i == t_frame//2 - 1),
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# LiteETHMACCRCEngine takes data LSB first
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self.crc.data.eq(Cat(reversed(sr_t[-2*n_mosi:]))),
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self.crca.data.eq(Cat([sri[-1] for sri in sr[::-1]])),
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self.crcb.data.eq(Cat([sri[-2] for sri in sr[::-1]])),
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self.crcb.last.eq(self.crca.next),
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miso_sr_next.eq(Cat(self.data[-1], miso_sr)),
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]
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self.sync.rio_phy += [
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@ -88,19 +93,20 @@ class SerDes(Module):
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clk.eq(Cat(clk[-2:], clk)),
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[sri.eq(Cat(C(0, 2), sri)) for sri in sr],
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miso_sr.eq(miso_sr_next),
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self.crc.last.eq(self.crc.next),
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self.crca.last.eq(self.crcb.next),
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i.eq(i + 1),
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If(self.stb,
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i.eq(0),
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clk.eq(clk.reset),
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self.crc.last.eq(0),
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self.crca.last.eq(0),
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# transpose, load
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[sri.eq(Cat(words[i::n_mosi])) for i, sri in enumerate(sr)],
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# unload miso
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self.readback.eq(Cat([miso_sr_next[t_miso + i*t_clk]
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for i in range(n_frame)])),
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# inject crc for the last cycle
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Cat(data_t[-n_crc:]).eq(self.crc.next),
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crc_insert.eq(self.crca.next if n_crc // n_mosi == 1
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else self.crcb.next),
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),
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]
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@ -114,14 +120,14 @@ class SerInterface(Module):
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[pins_n.clk] + list(pins_n.mosi)):
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ddr = Signal()
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self.specials += [
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# d1 closer to q, LSB first
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# d1 closer to q
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DDROutput(d[1], d[0], ddr, ClockSignal("rio_phy")),
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DifferentialOutput(ddr, pp, pn),
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]
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ddr = Signal()
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self.specials += [
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DifferentialInput(pins.miso, pins_n.miso, ddr),
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# q1 closer to d, MSB first
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DDRInput(ddr, self.data[-1][1], self.data[-1][0],
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# q1 closer to d
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DDRInput(ddr, self.data[-1][0], self.data[-1][1],
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ClockSignal("rio_phy")),
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]
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@ -16,27 +16,27 @@ class TestPhaser(unittest.TestCase):
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def record_frame(self, frame):
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clk = 0
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marker = 0
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state = "start"
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stb = 0
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while True:
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if stb == 2:
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frame.append((yield self.dut.data))
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clk = (clk << 2) & 0xff
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clk |= (yield self.dut.data[0])
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if clk == 0x0f:
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marker = (marker << 1) & 0x7f
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marker |= (yield self.dut.data[1]) & 1
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if marker >> 1 == 0x01:
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if state == "start":
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state = "end"
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elif state == "end":
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stb += 1
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if stb >= 3:
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break
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yield
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if state == "end":
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data = yield from [(yield d) for d in self.dut.data]
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frame.append(data)
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def test_frame(self):
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frame = []
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self.dut.comb += self.dut.payload.eq((1 << len(self.dut.payload)) - 1)
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run_simulation(self.dut, self.record_frame(frame),
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clocks={n: 2 for n in ["sys", "rio", "rio_phy"]})
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clocks={n: 2 for n in ["sys", "rio", "rio_phy"]},
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vcd_name="fastlink.vcd")
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self.assertEqual(len(frame), 8*10//2)
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self.assertEqual([d[0] for d in frame], [0, 0, 3, 3] * 10)
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self.assertEqual([d[1] & 1 for d in frame[4*4 - 1:10*4 - 1:4]],
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