forked from M-Labs/artiq
phaser: documentation
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@ -1,5 +1,3 @@
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import numpy as np
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from artiq.language.core import kernel, delay_mu, delay
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from artiq.coredevice.rtio import rtio_output, rtio_input_data
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from artiq.language.units import us, ns
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@ -49,44 +47,86 @@ PHASER_STA_TERM0 = 1 << 3
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PHASER_STA_TERM1 = 1 << 4
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PHASER_STA_SPI_IDLE = 1 << 5
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PHASER_DAC_SEL_DUC = 0
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PHASER_DAC_SEL_TEST = 1
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class Phaser:
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kernel_invariants = {"core", "channel_base", "t_frame"}
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"""Phaser 4-channel, 16-bit, 1 GS/s DAC coredevice driver.
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def __init__(self, dmgr, channel_base, miso_delay=1,
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core_device="core"):
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Phaser contains a 4 channel, 1 GS/s DAC chip with integrated upconversion,
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quadrature modulation compensation and interpolation features.
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The coredevice produces 2 IQ data streams with 25 MS/s 14 bit. Each
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data stream supports 5 independent numerically controlled oscillators (NCOs)
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added together for each channel. Together with a data clock, framing
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marker, a checksum and metadata for register access the data is sent in
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groups of 8 samples over 1.5 Gb/s FastLink via a single EEM connector.
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On Phaser the data streams are buffered and interpolated from 25 MS/s to 500
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MS/s 16 bit followed by a 500 MS/s digital upconverter in the FPGA.
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The four 16 bit 500 MS/s DAC data streams are sent via a 32 bit parallel
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LVDS bus operating at 1 Gb/s per pin pair and processed in the DAC.
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The four analog DAC outputs are passed through anti-aliasing filters and In
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the baseband variant, the even channels feed 31.5 dB range and are
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available on the front panel. The odd outputs are available on MMCX
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connectors on board.
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In the upconverter variant, each of the two IQ (in-phase and quadrature)
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output pairs feeds a one quadrature upconverter with integrated PLL/VCO.
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The output from the upconverter passes through the step attenuator and is
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available at the front panel.
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The DAC, the TRF upconverters and the two attenuators are configured
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through a shared SPI bus that is accessed and controlled via FPGA
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registers.
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:param channel: Base RTIO channel number
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:param core_device: Core device name (default: "core")
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:param miso_delay: Fastlink MISO signal delay to account for cable
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and buffer round trip. This might be automated later.
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"""
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kernel_invariants = {"core", "channel_base", "t_frame", "miso_delay"}
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def __init__(self, dmgr, channel_base, miso_delay=1, core_device="core"):
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self.channel_base = channel_base
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self.core = dmgr.get(core_device)
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self.miso_delay = miso_delay
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# frame duration in mu (10 words, 8 clock cycles each 4 ns)
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# self.core.seconds_to_mu(10*8*4*ns) # unfortunately 319
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# self.core.seconds_to_mu(10*8*4*ns) # unfortunately this returns 319
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assert self.core.ref_period == 1*ns
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self.t_frame = 10*8*4
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@kernel
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def init(self):
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"""Initialize the board.
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Verifies board presence by reading the board ID register.
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Does not alter any state.
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"""
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board_id = self.read8(PHASER_ADDR_BOARD_ID)
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if board_id != PHASER_BOARD_ID:
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raise ValueError("invalid board id")
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delay(20*us)
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delay(20*us) # slack
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@kernel
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def write8(self, addr, data):
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"""Write data to a Phaser FPGA register.
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"""Write data to FPGA register.
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:param addr: Address to write to.
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:param data: Data to write.
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:param addr: Address to write to (7 bit)
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:param data: Data to write (8 bit)
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"""
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rtio_output((self.channel_base << 8) | (addr & 0x7f) | 0x80, data)
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delay_mu(int64(self.t_frame))
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@kernel
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def read8(self, addr) -> TInt32:
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"""Read from Phaser FPGA register.
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"""Read from FPGA register.
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TODO: untested
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:param addr: Address to read from.
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:return: The data read.
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:param addr: Address to read from (7 bit)
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:return: Data read (8 bit)
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"""
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rtio_output((self.channel_base << 8) | (addr & 0x7f), 0)
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response = rtio_input_data(self.channel_base)
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@ -94,6 +134,7 @@ class Phaser:
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@kernel
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def write32(self, addr, data: TInt32):
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"""Write 32 bit to a sequence of FPGA registers."""
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for offset in range(4):
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byte = data >> 24
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self.write8(addr + offset, byte)
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@ -101,6 +142,7 @@ class Phaser:
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@kernel
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def read32(self, addr) -> TInt32:
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"""Read 32 bit from a sequence of FPGA registers."""
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data = 0
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for offset in range(4):
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data <<= 8
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@ -110,39 +152,80 @@ class Phaser:
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@kernel
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def write16(self, addr, data: TInt32):
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"""Write 16 bit to a sequence of FPGA registers."""
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self.write8(addr, data >> 8)
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self.write8(addr + 1, data)
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@kernel
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def read16(self, addr) -> TInt32:
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"""Read 16 bit from a sequence of FPGA registers."""
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return (self.read8(addr) << 8) | self.read8(addr)
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@kernel
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def set_leds(self, leds):
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"""Set the front panel LEDs.
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:param leds: LED settings (6 bit)
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"""
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self.write8(PHASER_ADDR_LED, leds)
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@kernel
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def set_fan(self, duty):
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"""Set the fan duty cycle.
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:param duty: Duty cycle (8 bit)
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"""
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self.write8(PHASER_ADDR_FAN, duty)
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@kernel
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def set_cfg(self, clk_sel=0, dac_resetb=1, dac_sleep=0, dac_txena=1,
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trf0_ps=0, trf1_ps=0, att0_rstn=1, att1_rstn=1):
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"""Set the configuration register.
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:param clk_sel: Select the external SMA clock input
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:param dac_resetb: Active low DAC reset pin
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:param dac_sleep: DAC sleep pin
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:param dac_txena: Enable DAC transmission pin
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:param trf0_ps: TRF0 upconverter power save
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:param trf1_ps: TRF1 upconverter power save
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:param att0_rstn: Active low attenuator 0 reset
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:param att1_rstn: Active low attenuator 1 reset
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"""
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self.write8(PHASER_ADDR_CFG,
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(clk_sel << 0) | (dac_resetb << 1) | (dac_sleep << 2) |
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(dac_txena << 3) | (trf0_ps << 4) | (trf1_ps << 5) |
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(att0_rstn << 6) | (att1_rstn << 7))
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(clk_sel << 0) | (dac_resetb << 1) | (dac_sleep << 2) |
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(dac_txena << 3) | (trf0_ps << 4) | (trf1_ps << 5) |
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(att0_rstn << 6) | (att1_rstn << 7))
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@kernel
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def get_sta(self):
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"""Get the status register value.
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Bit flags are:
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* `PHASER_STA_DAC_ALARM`: DAC alarm pin
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* `PHASER_STA_TRF0_LD`: TRF0 lock detect pin
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* `PHASER_STA_TRF1_LD`: TRF1 lock detect pin
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* `PHASER_STA_TERM0`: ADC channel 0 termination indicator
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* `PHASER_STA_TERM1`: ADC channel 1 termination indicator
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* `PHASER_STA_SPI_IDLE`: SPI machine is idle and data registers can be
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read/written
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:return: Status register
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"""
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return self.read8(PHASER_ADDR_STA)
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@kernel
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def get_crc_err(self):
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"""Get the frame CRC error counter."""
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return self.read8(PHASER_ADDR_CRC_ERR)
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@kernel
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def get_dac_data(self, ch) -> TInt32:
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"""Get a sample of the current DAC data.
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:param ch: DAC channel pair (0 or 1)
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:return: DAC data as 32 bit IQ
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"""
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data = 0
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for addr in range(4):
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data <<= 8
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@kernel
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def set_dac_test(self, ch, data: TInt32):
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"""Set the DAC test data.
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:param ch: DAC channel pair (0 or 1)
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:param data: 32 bit IQ test data
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"""
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for addr in range(4):
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byte = data >> 24
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self.write8(PHASER_ADDR_DAC0_TEST + (ch << 4) + addr, byte)
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@kernel
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def set_duc_cfg(self, ch, clr=0, clr_once=0, select=0):
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"""Set the digital upconverter and interpolator configuration.
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:param ch: DAC channel pair (0 or 1)
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:param clr: Keep the phase accumulator cleared
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:param clr_once: Clear the phase accumulator for one cycle
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:param select: Select the data to send to the DAC (0: DUC data, 1: test
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data)
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"""
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self.write8(PHASER_ADDR_DUC0_CFG + (ch << 4),
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(clr << 0) | (clr_once << 1) | (select << 2))
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(clr << 0) | (clr_once << 1) | (select << 2))
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@kernel
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def set_duc_frequency_mu(self, ch, ftw):
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"""Set the DUC frequency.
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:param ch: DAC channel pair (0 or 1)
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:param ftw: DUC frequency tuning word
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"""
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self.write32(PHASER_ADDR_DUC0_F + (ch << 4), ftw)
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@kernel
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def set_duc_phase_mu(self, ch, pow):
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"""Set the DUC phase offset
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:param ch: DAC channel pair (0 or 1)
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:param pow: DUC phase offset word
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"""
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self.write16(PHASER_ADDR_DUC0_P + (ch << 4), pow)
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@kernel
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def duc_stb(self):
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"""Strobe the DUC configuration register update.
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Transfer staging to active registers.
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This affects both DUC channels.
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"""
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self.write8(PHASER_ADDR_DUC_STB, 0)
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@kernel
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def spi_cfg(self, select, div, end, clk_phase=0, clk_polarity=0,
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half_duplex=0, lsb_first=0, offline=0, length=8):
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"""Set the SPI machine configuration
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:param select: Chip selects to assert (DAC, TRF0, TRF1, ATT0, ATT1)
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:param div: SPI clock divider relative to 250 MHz fabric clock
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:param end: Whether to end the SPI transaction and deassert chip select
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:param clk_phase: SPI clock phase (sample on first or second edge)
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:param clk_polarity: SPI clock polarity (idle low or high)
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:param half_duplex: Read MISO data from MOSI wire
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:param lsb_first: Transfer the least significant bit first
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:param offline: Put the SPI interfaces offline and don't drive voltages
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:param length: SPI transfer length (1 to 8 bits)
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"""
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self.write8(PHASER_ADDR_SPI_SEL, select)
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self.write8(PHASER_ADDR_SPI_DIVLEN, (div - 2 >> 3) | (length - 1 << 5))
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self.write8(PHASER_ADDR_SPI_CFG,
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(offline << 0) | (end << 1) | (clk_phase << 2) |
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(clk_polarity << 3) | (half_duplex << 4) |
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(lsb_first << 5))
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(offline << 0) | (end << 1) | (clk_phase << 2) |
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(clk_polarity << 3) | (half_duplex << 4) |
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(lsb_first << 5))
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@kernel
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def spi_write(self, data):
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"""Write 8 bits into the SPI data register and start/continue the
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transaction."""
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self.write8(PHASER_ADDR_SPI_DATW, data)
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@kernel
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def spi_read(self):
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"""Read from the SPI input data register."""
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return self.read8(PHASER_ADDR_SPI_DATR)
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@kernel
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def dac_write(self, addr, data):
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"""Write 16 bit to a DAC register.
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:param addr: Register address
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:param data: Register data to write
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"""
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div = 32 # 100 ns min period
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t_xfer = self.core.seconds_to_mu((8 + 1)*div*4*ns)
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self.spi_cfg(select=PHASER_SEL_DAC, div=div, end=0)
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@kernel
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def dac_read(self, addr, div=32) -> TInt32:
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"""Read from a DAC register.
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:param addr: Register address to read from
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:param div: SPI clock divider. Needs to be at least 250 to read the
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temperature register.
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"""
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t_xfer = self.core.seconds_to_mu((8 + 1)*div*4*ns)
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self.spi_cfg(select=PHASER_SEL_DAC, div=div, end=0)
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self.spi_write(addr | 0x80)
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@kernel
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def att_write(self, ch, data):
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"""Set channel attenuation.
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:param ch: RF channel (0 or 1)
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:param data: Attenuator data
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"""
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div = 32 # 30 ns min period
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t_xfer = self.core.seconds_to_mu((8 + 1)*div*4*ns)
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self.spi_cfg(select=PHASER_SEL_ATT0 << ch, div=div, end=1)
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@kernel
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def att_read(self, ch) -> TInt32:
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"""Read current attenuation.
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The current attenuation value is read without side effects.
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:param ch: RF channel (0 or 1)
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:return: Current attenuation
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"""
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div = 32
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t_xfer = self.core.seconds_to_mu((8 + 1)*div*4*ns)
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self.spi_cfg(select=PHASER_SEL_ATT0 << ch, div=div, end=0)
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@kernel
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def trf_write(self, ch, data, readback=False):
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"""Write 32 bits to a TRF upconverter.
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:param ch: RF channel (0 or 1)
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:param data: Register data (32 bit)
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:param readback: Whether to return the read back MISO data
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"""
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div = 32 # 50 ns min period
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t_xfer = self.core.seconds_to_mu((8 + 1)*div*4*ns)
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read = 0
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@kernel
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def trf_read(self, ch, addr, cnt_mux_sel=0) -> TInt32:
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"""TRF upconverter register read.
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:param ch: RF channel (0 or 1)
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:param addr: Register address to read
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:param cnt_mux_sel: Report VCO counter min frequency
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or max frequency
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:return: Register data (32 bit)
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"""
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self.trf_write(ch, 0x80000008 | (addr << 28) | (cnt_mux_sel << 27))
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# single clk pulse to start readback
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# single clk pulse with ~LE to start readback
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self.spi_cfg(select=0, div=32, end=1, length=1)
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self.spi_write(0)
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delay((1 + 1)*32*4*ns)
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@kernel
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def set_frequency_mu(self, ch, osc, ftw):
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"""Set Phaser MultiDDS frequency tuning word.
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:param ch: RF channel (0 or 1)
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:param osc: Oscillator number (0 to 4)
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:param ftw: Frequency tuning word (32 bit)
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"""
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addr = ((self.channel_base + 1 + ch) << 8) | (osc << 1)
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rtio_output(addr, ftw)
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@kernel
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def set_amplitude_phase_mu(self, ch, osc, asf=0x7fff, pow=0, clr=0):
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"""Set Phaser MultiDDS amplitude, phase offset and accumulator clear.
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:param ch: RF channel (0 or 1)
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:param osc: Oscillator number (0 to 4)
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:param asf: Amplitude (15 bit)
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:param pow: Phase offset word (16 bit)
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:param clr: Clear the phase accumulator (persistent)
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"""
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addr = ((self.channel_base + 1 + ch) << 8) | (osc << 1) | 1
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data = (asf & 0x7fff) | (clr << 15) | (pow << 16)
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rtio_output(addr, data)
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enable_replace=False),
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rtlink.IInterface(data_width=10))
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# share a CosSinGen LUT between the two channels
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self.submodules.ch0 = DDSChannel()
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self.submodules.ch1 = DDSChannel(use_lut=self.ch0.dds.mod.cs.lut)
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n_channels = 2
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@ -38,7 +39,7 @@ class Phaser(Module):
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body = Signal(n_samples*n_channels*2*n_bits, reset_less=True)
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self.sync.rio_phy += [
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If(self.ch0.dds.valid, # & self.ch1.dds.valid,
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# recent sample, ch0, i first
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# recent:ch0:i as low order in body
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Cat(body).eq(Cat(self.ch0.dds.o.i[2:], self.ch0.dds.o.q[2:],
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self.ch1.dds.o.i[2:], self.ch1.dds.o.q[2:],
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body)),
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@ -66,7 +67,7 @@ class Phaser(Module):
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re_dly = Signal(3) # stage, send, respond
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self.sync.rtio += [
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header.type.eq(1), # reserved
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header.type.eq(1), # body type is baseband data
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If(self.serializer.stb,
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self.ch0.dds.stb.eq(1), # synchronize
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self.ch1.dds.stb.eq(1), # synchronize
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@ -130,6 +130,11 @@ RF generation drivers
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.. automodule:: artiq.coredevice.basemod_att
|
||||
:members:
|
||||
|
||||
:mod:`artiq.coredevice.phaser` module
|
||||
+++++++++++++++++++++++++++++++++++++
|
||||
|
||||
.. automodule:: artiq.coredevice.phaser
|
||||
:members:
|
||||
|
||||
DAC/ADC drivers
|
||||
---------------
|
||||
|
|
Loading…
Reference in New Issue