forked from M-Labs/artiq
rtio/dma: fix previous commit
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f2e0d27334
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@ -12,7 +12,7 @@ def _reverse_bytes(s, g):
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class WishboneReader(Module):
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def __init__(self):
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def __init__(self, bus):
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self.bus = bus
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aw = len(bus.adr)
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