forked from M-Labs/artiq
kasli2: forward sma_clkin to si5324
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parent
bff611a888
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29c940f4e3
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@ -79,6 +79,21 @@ class _RTIOCRG(Module, AutoCSR):
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]
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class SMAClkinForward(Module):
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def __init__(self, platform):
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sma_clkin = platform.request("sma_clkin")
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sma_clkin_se = Signal()
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sma_clkin_buffered = Signal()
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cdr_clk_se = Signal()
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cdr_clk = platform.request("cdr_clk")
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self.specials += [
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Instance("IBUFDS", i_I=sma_clkin.p, i_IB=sma_clkin.n, o_O=sma_clkin_se),
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Instance("BUFIO", i_I=sma_clkin_se, o_O=sma_clkin_buffered),
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Instance("ODDR", i_C=sma_clkin_buffered, i_CE=1, i_D1=0, i_D2=1, o_Q=cdr_clk_se),
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Instance("OBUFDS", i_I=cdr_clk_se, o_O=cdr_clk.p, o_OB=cdr_clk.n)
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]
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def fix_serdes_timing_path(platform):
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# ignore timing of path from OSERDESE2 through the pad to ISERDESE2
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platform.add_platform_command(
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@ -115,6 +130,7 @@ class StandaloneBase(MiniSoC, AMPSoC):
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self.submodules.error_led = gpio.GPIOOut(Cat(
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self.platform.request("error_led")))
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self.csr_devices.append("error_led")
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self.submodules += SMAClkinForward(self.platform)
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i2c = self.platform.request("i2c")
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self.submodules.i2c = gpio.GPIOTristate([i2c.scl, i2c.sda])
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@ -294,6 +310,9 @@ class MasterBase(MiniSoC, AMPSoC):
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platform = self.platform
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if platform.hw_rev == "v2.0":
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self.submodules += SMAClkinForward(platform)
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i2c = self.platform.request("i2c")
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self.submodules.i2c = gpio.GPIOTristate([i2c.scl, i2c.sda])
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self.csr_devices.append("i2c")
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